For parts like the STM32F1 Connectivity Line (STM32F105xx, STM32F107xx),
it is occasionally necessary to source SYSCLK via PLL2. This patch will
add this support.
- Add: `UTILS_GetPLL2OutputFrequency()` to calculate the output frequency of PLL2
- Add: `LL_PLL_ConfigSystemClock_PLL2()` to configure the system clock as sourced from HSE, via PLL2 and PLL1.
- Add: Miscellaneous support definitions.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Cervac Petru
Attie Grande
Eya
rihab kouki
Ali Labbene
Christophe Cadoret