1196 lines
52 KiB
C
1196 lines
52 KiB
C
/**
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******************************************************************************
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* @file Examples_LL/ADC/ADC_MultimodeDualInterleaved/Src/main.c
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* @author MCD Application Team
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* @brief This example describes how to use several ADC peripherals in
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* multimode, mode interleaved.
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* ADC master instance synchronizes and manages ADC slave instance.
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* Multimode interleaved combines ADC instances to convert
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* the same channel and increase the overall ADC conversion rate.
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* This example configures the ADC to perform conversions at the
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* maximum ADC conversion rate possible (with a sampling time
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* corresponding to ADC resolution 12 bits).
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* This example is based on the STM32F1xx ADC LL API;
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* Peripheral initialization done using LL unitary services functions.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "main.h"
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/** @addtogroup STM32F1xx_LL_Examples
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* @{
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*/
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/** @addtogroup ADC_MultimodeDualInterleaved
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Definitions of ADC hardware constraints delays */
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/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
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/* not timeout values: */
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/* Timeout values for ADC operations are dependent to device clock */
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/* configuration (system clock versus ADC clock), */
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/* and therefore must be defined in user application. */
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/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
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/* values definition. */
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/* Timeout values for ADC operations. */
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/* (enable settling time, disable settling time, ...) */
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/* Values defined to be higher than worst cases: low clock frequency, */
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/* maximum prescalers. */
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/* Example of profile very low frequency : ADC clock frequency 12MHz */
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/* prescaler 6, sampling time 1.5 ADC clock cycles, resolution 12 bits. */
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/* - ADC enable time: maximum delay is 1 us */
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/* (refer to device datasheet, parameter "tSTAB") */
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/* - ADC disable time: maximum delay should be a few ADC clock cycles */
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/* - ADC stop conversion time: maximum delay should be a few ADC clock */
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/* cycles */
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/* - ADC conversion time: with this hypothesis of clock settings, maximum */
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/* delay will be 7us. */
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/* (refer to device reference manual, section "Timing") */
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/* Unit: ms */
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#define ADC_CALIBRATION_TIMEOUT_MS ((uint32_t) 1)
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#define ADC_ENABLE_TIMEOUT_MS ((uint32_t) 1)
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#define ADC_DISABLE_TIMEOUT_MS ((uint32_t) 1)
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#define ADC_STOP_CONVERSION_TIMEOUT_MS ((uint32_t) 1)
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#define ADC_CONVERSION_TIMEOUT_MS ((uint32_t) 2)
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/* Delay between ADC enable and ADC end of calibration. */
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/* Delay estimation in CPU cycles: Case of ADC calibration done */
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/* immediately after ADC enable, ADC clock setting slow */
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/* (LL_ADC_CLOCK_ASYNC_DIV32). Use a higher delay if ratio */
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/* (CPU clock / ADC clock) is above 32. */
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#define ADC_DELAY_ENABLE_CALIB_CPU_CYCLES (LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES * 32)
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/* Definitions of environment analog values */
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/* Value of analog reference voltage (Vref+), connected to analog voltage */
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/* supply Vdda (unit: mV). */
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#define VDDA_APPLI ((uint32_t)3300)
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/* Definitions of data related to this example */
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/* Init variable out of expected ADC conversion data range */
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#define VAR_CONVERTED_DATA_INIT_VALUE (__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)
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/* Definition of ADCx conversions data table size */
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/* Note: Considering interruption occurring after each number of */
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/* "ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions */
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/* (IT from DMA transfer complete), */
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/* select sampling time and ADC clock with sufficient */
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/* duration to not create an overhead situation in IRQHandler. */
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#define ADC_CONVERTED_DATA_BUFFER_SIZE ((uint32_t) 256)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Variables for ADC conversion data */
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__IO uint32_t aADCxADCyMultimodeDualConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* ADC multimode dual conversion data: ADC master and ADC slave conversion data are concatenated in a registers of 32 bits. */
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static uint16_t aADCxMultimodeDualMasterConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];/* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC master conversion data. */
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static uint16_t aADCyMultimodeDualSlaveConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC slave conversion data. */
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/* Variable to report status of DMA transfer of ADC group regular conversions */
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/* 0: DMA transfer is not completed */
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/* 1: DMA transfer is completed */
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/* 2: DMA transfer has not been started yet (initial state) */
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__IO uint8_t ubDmaTransferStatus = 2; /* Variable set into DMA interruption callback */
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/* Private function prototypes -----------------------------------------------*/
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void SystemClock_Config(void);
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void Configure_DMA(void);
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void Configure_ADC(void);
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void Configure_ADC_slave(void);
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void Activate_ADC(void);
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void Activate_ADC_slave(void);
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void LED_Init(void);
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void LED_On(void);
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void LED_Off(void);
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void LED_Blinking(uint32_t Period);
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void UserButton_Init(void);
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/* Private functions ---------------------------------------------------------*/
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/**
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* @brief Main program
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* @param None
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* @retval None
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*/
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int main(void)
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{
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/* Configure the system clock to 72 MHz */
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SystemClock_Config();
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/* Initialize LED2 */
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LED_Init();
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/* Initialize button in EXTI mode */
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UserButton_Init();
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/* Configure DMA for data transfer from ADC */
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Configure_DMA();
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/* Configure ADC */
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/* Note: This function configures the ADC but does not enable it. */
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/* To enable it, use function "Activate_ADC()". */
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/* This is intended to optimize power consumption: */
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/* 1. ADC configuration can be done once at the beginning */
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/* (ADC disabled, minimal power consumption) */
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/* 2. ADC enable (higher power consumption) can be done just before */
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/* ADC conversions needed. */
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/* Then, possible to perform successive "Activate_ADC()", */
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/* "Deactivate_ADC()", ..., without having to set again */
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/* ADC configuration. */
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Configure_ADC();
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/* For multimode, configure ADC slave */
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Configure_ADC_slave();
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/* Activate ADC */
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/* Perform ADC activation procedure to make it ready to convert. */
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Activate_ADC();
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Activate_ADC_slave();
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/* Infinite loop */
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while (1)
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{
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/* Note: ADC group regular conversion start is done into push button */
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/* IRQ handler, refer to function "UserButton_Callback()". */
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/* Note: LED state depending on DMA transfer status is set into DMA */
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/* IRQ handler, refer to functions "DmaTransferComplete()" */
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/* and "DmaTransferHalfComplete()". */
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/* Note: ADC conversion data are stored into array */
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/* "aADCxADCyMultimodeDualConvertedData". */
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/* For this example purpose, ADC conversion data of ADC master and */
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/* ADC slave are dispatched into arrays */
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/* "aADCxMultimodeDualMasterConvertedData" */
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/* and "aADCyMultimodeDualSlaveConvertedData", refer to comments */
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/* into function "DmaTransferComplete()". */
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/* (for debug: see variable content into watch window). */
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/* Note: ADC conversion data can be computed to physical values */
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/* using ADC LL driver helper macro: */
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/* uhADCxConvertedData_Voltage_mVolt */
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/* = __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI, */
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/* uhADCxConvertedData), */
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/* LL_ADC_RESOLUTION_12B) */
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}
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}
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/**
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* @brief This function configures DMA for transfer of data from ADC
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* @param None
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* @retval None
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*/
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void Configure_DMA(void)
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{
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/*## Configuration of NVIC #################################################*/
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/* Configure NVIC to enable DMA interruptions */
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NVIC_SetPriority(DMA1_Channel1_IRQn, 1); /* DMA IRQ lower priority than ADC IRQ */
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NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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/*## Configuration of DMA ##################################################*/
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/* Enable the peripheral clock of DMA */
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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/* Configure the DMA transfer */
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/* - DMA transfer in circular mode to match with ADC configuration: */
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/* DMA unlimited requests. */
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/* - DMA transfer from ADC without address increment. */
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/* - DMA transfer to memory with address increment. */
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/* - DMA transfer from ADC by word to match with ADC configuration: */
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/* ADC resolution 12 bits and and multimode enabled, */
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/* ADC master and ADC slave conversion data are concatenated in */
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/* a register of 32 bits. */
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/* - DMA transfer to memory by word to match with ADC conversion data */
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/* buffer variable type: word. */
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LL_DMA_ConfigTransfer(DMA1,
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LL_DMA_CHANNEL_1,
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LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
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LL_DMA_MODE_CIRCULAR |
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LL_DMA_PERIPH_NOINCREMENT |
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LL_DMA_MEMORY_INCREMENT |
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LL_DMA_PDATAALIGN_WORD |
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LL_DMA_MDATAALIGN_WORD |
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LL_DMA_PRIORITY_HIGH );
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/* Set DMA transfer addresses of source and destination */
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/* Note: On this STM32 device, in multimode, ADC conversion data with */
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/* ADC master and ADC slave conversion data concatenated are located */
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/* in data register of ADC master. */
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LL_DMA_ConfigAddresses(DMA1,
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LL_DMA_CHANNEL_1,
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LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
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(uint32_t)&aADCxADCyMultimodeDualConvertedData,
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LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
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/* Set DMA transfer size */
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LL_DMA_SetDataLength(DMA1,
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LL_DMA_CHANNEL_1,
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ADC_CONVERTED_DATA_BUFFER_SIZE);
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/* Enable DMA transfer interruption: transfer complete */
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LL_DMA_EnableIT_TC(DMA1,
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LL_DMA_CHANNEL_1);
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/* Enable DMA transfer interruption: half transfer */
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LL_DMA_EnableIT_HT(DMA1,
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LL_DMA_CHANNEL_1);
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/* Enable DMA transfer interruption: transfer error */
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LL_DMA_EnableIT_TE(DMA1,
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LL_DMA_CHANNEL_1);
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/*## Activation of DMA #####################################################*/
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/* Enable the DMA transfer */
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LL_DMA_EnableChannel(DMA1,
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LL_DMA_CHANNEL_1);
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}
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/**
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* @brief Configure ADC (ADC instance: ADC1) and GPIO used by ADC channels.
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* @note In case re-use of this function outside of this example:
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* This function includes checks of ADC hardware constraints before
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* executing some configuration functions.
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* - In this example, all these checks are not necessary but are
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* implemented anyway to show the best practice usages
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* corresponding to reference manual procedure.
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* (On some STM32 series, setting of ADC features are not
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* conditioned to ADC state. However, in order to be compliant with
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* other STM32 series and to show the best practice usages,
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* ADC state is checked anyway with same constraints).
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* Software can be optimized by removing some of these checks,
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* if they are not relevant considering previous settings and actions
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* in user application.
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* - If ADC is not in the appropriate state to modify some parameters,
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* the setting of these parameters is bypassed without error
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* reporting:
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* it can be the expected behavior in case of recall of this
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* function to update only a few parameters (which update fullfills
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* the ADC state).
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* Otherwise, it is up to the user to set the appropriate error
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* reporting in user application.
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* @note Peripheral configuration is minimal configuration from reset values.
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* Thus, some useless LL unitary functions calls below are provided as
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* commented examples - setting is default configuration from reset.
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* @param None
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* @retval None
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*/
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void Configure_ADC(void)
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{
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/*## Configuration of GPIO used by ADC channels ############################*/
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/* Note: On this STM32 device, ADC1 channel 4 is mapped on GPIO pin PA.04 */
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/* Enable GPIO Clock */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
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/* Configure GPIO in analog mode to be used as ADC input */
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LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_4, LL_GPIO_MODE_ANALOG);
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/*## Configuration of NVIC #################################################*/
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/* Configure NVIC to enable ADC1 interruptions */
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NVIC_SetPriority(ADC1_2_IRQn, 0); /* ADC IRQ greater priority than DMA IRQ */
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NVIC_EnableIRQ(ADC1_2_IRQn);
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/*## Configuration of ADC ##################################################*/
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/*## Configuration of ADC hierarchical scope: common to several ADC ########*/
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/* Enable ADC clock (core clock) */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);
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/* Note: Hardware constraint (refer to description of the functions */
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/* below): */
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/* On this STM32 serie, setting of these features are not */
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/* conditioned to ADC state. */
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/* However, in order to be compliant with other STM32 series */
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/* and to show the best practice usages, ADC state is checked. */
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/* Software can be optimized by removing some of these checks, if */
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/* they are not relevant considering previous settings and actions */
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/* in user application. */
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if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() == 0)
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{
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/* Note: Call of the functions below are commented because they are */
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/* useless in this example: */
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/* setting corresponding to default configuration from reset state. */
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/* Set ADC measurement path to internal channels */
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// LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_PATH_INTERNAL_NONE);
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/*## Configuration of ADC hierarchical scope: multimode ####################*/
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/* Set ADC multimode configuration */
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LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_DUAL_REG_INTERL_FAST);
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}
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/*## Configuration of ADC hierarchical scope: ADC instance #################*/
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/* Note: Hardware constraint (refer to description of the functions */
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/* below): */
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/* On this STM32 serie, setting of these features are not */
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/* conditioned to ADC state. */
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/* However, ADC state is checked anyway with standard requirements */
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/* (refer to description of this function). */
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if (LL_ADC_IsEnabled(ADC1) == 0)
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{
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/* Note: Call of the functions below are commented because they are */
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/* useless in this example: */
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/* setting corresponding to default configuration from reset state. */
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/* Set ADC conversion data alignment */
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// LL_ADC_SetResolution(ADC1, LL_ADC_DATA_ALIGN_RIGHT);
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/* Set Set ADC sequencers scan mode, for all ADC groups */
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/* (group regular, group injected). */
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// LL_ADC_SetSequencersScanMode(ADC1, LL_ADC_SEQ_SCAN_DISABLE);
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}
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/*## Configuration of ADC hierarchical scope: ADC group regular ############*/
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/* Note: Hardware constraint (refer to description of the functions */
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/* below): */
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/* On this STM32 serie, setting of these features are not */
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/* conditioned to ADC state. */
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/* However, ADC state is checked anyway with standard requirements */
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/* (refer to description of this function). */
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if (LL_ADC_IsEnabled(ADC1) == 0)
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{
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/* Set ADC group regular trigger source */
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LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);
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/* Set ADC group regular trigger polarity */
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// LL_ADC_REG_SetTriggerEdge(ADC1, LL_ADC_REG_TRIG_EXT_RISING);
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/* Set ADC group regular continuous mode */
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LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_CONTINUOUS);
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/* Set ADC group regular conversion data transfer */
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/* Note: Both ADC master and ADC slave have multimode setting */
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/* to use 1 DMA channel for all ADC instances. */
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/* In this case, each ADC Slave instance must have setting of */
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/* ADC DMA request set to default value (no DMA transfer). */
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/* and ADC DMA transfer is managed by ADC1 instance. */
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LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_UNLIMITED);
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/* Set ADC group regular sequencer */
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/* Note: On this STM32 serie, ADC group regular sequencer is */
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/* fully configurable: sequencer length and each rank */
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/* affectation to a channel are configurable. */
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/* Refer to description of function */
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/* "LL_ADC_REG_SetSequencerLength()". */
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/* Set ADC group regular sequencer length and scan direction */
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LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE);
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/* Set ADC group regular sequencer discontinuous mode */
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// LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE);
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/* Set ADC group regular sequence: channel on the selected sequence rank. */
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LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_4);
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}
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/*## Configuration of ADC hierarchical scope: ADC group injected ###########*/
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/* Note: Hardware constraint (refer to description of the functions */
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/* below): */
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/* On this STM32 serie, setting of these features are not */
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/* conditioned to ADC state. */
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/* However, ADC state is checked anyway with standard requirements */
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/* (refer to description of this function). */
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if (LL_ADC_IsEnabled(ADC1) == 0)
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{
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/* Note: Call of the functions below are commented because they are */
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/* useless in this example: */
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/* setting corresponding to default configuration from reset state. */
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/* Set ADC group injected trigger source */
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// LL_ADC_INJ_SetTriggerSource(ADC1, LL_ADC_INJ_TRIG_SOFTWARE);
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/* Set ADC group injected trigger polarity */
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// LL_ADC_INJ_SetTriggerEdge(ADC1, LL_ADC_INJ_TRIG_EXT_RISING);
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/* Set ADC group injected conversion trigger */
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// LL_ADC_INJ_SetTrigAuto(ADC1, LL_ADC_INJ_TRIG_INDEPENDENT);
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/* Set ADC group injected sequencer */
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/* Note: On this STM32 serie, ADC group injected sequencer is */
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/* fully configurable: sequencer length and each rank */
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/* affectation to a channel are configurable. */
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/* Refer to description of function */
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/* "LL_ADC_INJ_SetSequencerLength()". */
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/* Set ADC group injected sequencer length and scan direction */
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// LL_ADC_INJ_SetSequencerLength(ADC1, LL_ADC_INJ_SEQ_SCAN_DISABLE);
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/* Set ADC group injected sequencer discontinuous mode */
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// LL_ADC_INJ_SetSequencerDiscont(ADC1, LL_ADC_INJ_SEQ_DISCONT_DISABLE);
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/* Set ADC group injected sequence: channel on the selected sequence rank. */
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// LL_ADC_INJ_SetSequencerRanks(ADC1, LL_ADC_INJ_RANK_1, LL_ADC_CHANNEL_4);
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}
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/*## Configuration of ADC hierarchical scope: channels #####################*/
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/* Note: Hardware constraint (refer to description of the functions */
|
|
/* below): */
|
|
/* On this STM32 serie, setting of these features are not */
|
|
/* conditioned to ADC state. */
|
|
/* However, in order to be compliant with other STM32 series */
|
|
/* and to show the best practice usages, ADC state is checked. */
|
|
/* Software can be optimized by removing some of these checks, if */
|
|
/* they are not relevant considering previous settings and actions */
|
|
/* in user application. */
|
|
if (LL_ADC_IsEnabled(ADC1) == 0)
|
|
{
|
|
/* Set ADC channels sampling time */
|
|
/* Note: Considering interruption occurring after each number of */
|
|
/* "ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions */
|
|
/* (IT from DMA transfer complete), */
|
|
/* select sampling time and ADC clock with sufficient */
|
|
/* duration to not create an overhead situation in IRQHandler. */
|
|
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_4, LL_ADC_SAMPLINGTIME_1CYCLE_5);
|
|
|
|
}
|
|
|
|
|
|
/*## Configuration of ADC transversal scope: analog watchdog ###############*/
|
|
|
|
/* Note: On this STM32 serie, there is only 1 analog watchdog available. */
|
|
|
|
/* Set ADC analog watchdog: channels to be monitored */
|
|
// LL_ADC_SetAnalogWDMonitChannels(ADC1, LL_ADC_AWD_DISABLE);
|
|
|
|
/* Set ADC analog watchdog: thresholds */
|
|
// LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_THRESHOLD_HIGH, __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B));
|
|
// LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_THRESHOLD_LOW, 0x000);
|
|
|
|
|
|
/*## Configuration of ADC transversal scope: oversampling ##################*/
|
|
|
|
/* Note: Feature not available on this STM32 serie */
|
|
|
|
|
|
/*## Configuration of ADC interruptions ####################################*/
|
|
/* Note: In this example, no ADC interruption enabled */
|
|
|
|
/* Note: in this example, ADC group regular end of conversions */
|
|
/* (number of ADC conversions defined by DMA buffer size) */
|
|
/* are notified by DMA transfer interruptions). */
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief For multimode, configure ADC slave (ADC instance: ADC2)
|
|
* and GPIO used by ADC channels.
|
|
* @note Configuration of GPIO:
|
|
* Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
|
|
* Configuration of ADC:
|
|
* - Common to several ADC:
|
|
* Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
|
|
* - Multimode
|
|
* Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
|
|
* @note In case re-use of this function outside of this example:
|
|
* This function includes checks of ADC hardware constraints before
|
|
* executing some configuration functions.
|
|
* - In this example, all these checks are not necessary but are
|
|
* implemented anyway to show the best practice usages
|
|
* corresponding to reference manual procedure.
|
|
* (On some STM32 series, setting of ADC features are not
|
|
* conditioned to ADC state. However, in order to be compliant with
|
|
* other STM32 series and to show the best practice usages,
|
|
* ADC state is checked anyway with same constraints).
|
|
* Software can be optimized by removing some of these checks,
|
|
* if they are not relevant considering previous settings and actions
|
|
* in user application.
|
|
* - If ADC is not in the appropriate state to modify some parameters,
|
|
* the setting of these parameters is bypassed without error
|
|
* reporting:
|
|
* it can be the expected behavior in case of recall of this
|
|
* function to update only a few parameters (which update fullfills
|
|
* the ADC state).
|
|
* Otherwise, it is up to the user to set the appropriate error
|
|
* reporting in user application.
|
|
* @note Peripheral configuration is minimal configuration from reset values.
|
|
* Thus, some useless LL unitary functions calls below are provided as
|
|
* commented examples - setting is default configuration from reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void Configure_ADC_slave(void)
|
|
{
|
|
/*## Configuration of GPIO used by ADC channels ############################*/
|
|
/* Note: not configured: In this example, ADC slave group regular converts */
|
|
/* the same channel as ADC master group regular. */
|
|
/* Channel configuration same as ADC master. */
|
|
|
|
/*## Configuration of NVIC #################################################*/
|
|
/* Configure NVIC to enable ADC2 interruptions */
|
|
NVIC_SetPriority(ADC1_2_IRQn, 0); /* ADC IRQ greater priority than DMA IRQ */
|
|
NVIC_EnableIRQ(ADC1_2_IRQn);
|
|
|
|
/*## Configuration of ADC ##################################################*/
|
|
/* Enable ADC clock (core clock) */
|
|
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC2);
|
|
/*## Configuration of ADC hierarchical scope: common to several ADC ########*/
|
|
/* Note: ADC clock (core clock) not configured: same as ADC master */
|
|
/* (ADC slave shares the common clock of ADC master). */
|
|
/* Note: not configured: same as ADC master (ADC slave shares the common */
|
|
/* configuration of ADC master). */
|
|
|
|
/*## Configuration of ADC hierarchical scope: multimode ####################*/
|
|
/* Note: not configured: same as ADC master (ADC slave shares the common */
|
|
/* configuration of ADC master). */
|
|
|
|
|
|
/*## Configuration of ADC hierarchical scope: ADC instance #################*/
|
|
|
|
/* Note: Hardware constraint (refer to description of the functions */
|
|
/* below): */
|
|
/* On this STM32 serie, setting of these features are not */
|
|
/* conditioned to ADC state. */
|
|
/* However, ADC state is checked anyway with standard requirements */
|
|
/* (refer to description of this function). */
|
|
if (LL_ADC_IsEnabled(ADC2) == 0)
|
|
{
|
|
/* Note: Call of the functions below are commented because they are */
|
|
/* useless in this example: */
|
|
/* setting corresponding to default configuration from reset state. */
|
|
|
|
/* Set ADC conversion data alignment */
|
|
// LL_ADC_SetResolution(ADC2, LL_ADC_DATA_ALIGN_RIGHT);
|
|
|
|
/* Set Set ADC sequencers scan mode, for all ADC groups */
|
|
/* (group regular, group injected). */
|
|
LL_ADC_SetSequencersScanMode(ADC2, LL_ADC_SEQ_SCAN_ENABLE);
|
|
|
|
}
|
|
|
|
|
|
/*## Configuration of ADC hierarchical scope: ADC group regular ############*/
|
|
|
|
/* Note: Hardware constraint (refer to description of the functions */
|
|
/* below): */
|
|
/* On this STM32 serie, setting of these features are not */
|
|
/* conditioned to ADC state. */
|
|
/* However, ADC state is checked anyway with standard requirements */
|
|
/* (refer to description of this function). */
|
|
if (LL_ADC_IsEnabled(ADC2) == 0)
|
|
{
|
|
/* Set ADC group regular trigger source */
|
|
/* Note: On this STM32 device, in multimode, ADC slave trigger source */
|
|
/* setting is mandatory: SW start. */
|
|
LL_ADC_REG_SetTriggerSource(ADC2, LL_ADC_REG_TRIG_SOFTWARE);
|
|
|
|
/* Set ADC group regular continuous mode */
|
|
/* Note: On this STM32 device, in multimode, ADC slave continuous */
|
|
/* conversions mode must be the same as ADC master. */
|
|
LL_ADC_REG_SetContinuousMode(ADC2, LL_ADC_REG_CONV_CONTINUOUS);
|
|
|
|
/* Set ADC group regular conversion data transfer */
|
|
/* Note: Both ADC master and ADC slave have multimode setting */
|
|
/* to use 1 DMA channel for all ADC instances. */
|
|
/* In this case, each ADC Slave instance must have setting of */
|
|
/* ADC DMA request set to default value (no DMA transfer). */
|
|
/* and ADC DMA transfer is managed by ADC1 instance. */
|
|
LL_ADC_REG_SetDMATransfer(ADC2, LL_ADC_REG_DMA_TRANSFER_NONE);
|
|
|
|
/* Set ADC group regular sequencer */
|
|
/* Note: On this STM32 serie, ADC group regular sequencer is */
|
|
/* fully configurable: sequencer length and each rank */
|
|
/* affectation to a channel are configurable. */
|
|
/* Refer to description of function */
|
|
/* "LL_ADC_REG_SetSequencerLength()". */
|
|
|
|
/* Set ADC group regular sequencer length and scan direction */
|
|
LL_ADC_REG_SetSequencerLength(ADC2, LL_ADC_REG_SEQ_SCAN_DISABLE);
|
|
|
|
/* Set ADC group regular sequencer discontinuous mode */
|
|
// LL_ADC_REG_SetSequencerDiscont(ADC2, LL_ADC_REG_SEQ_DISCONT_DISABLE);
|
|
|
|
/* Set ADC group regular sequence: channel on the selected sequence rank. */
|
|
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_4);
|
|
}
|
|
|
|
|
|
/*## Configuration of ADC hierarchical scope: ADC group injected ###########*/
|
|
|
|
/* Note: Hardware constraint (refer to description of the functions */
|
|
/* below): */
|
|
/* On this STM32 serie, setting of these features are not */
|
|
/* conditioned to ADC state. */
|
|
/* However, ADC state is checked anyway with standard requirements */
|
|
/* (refer to description of this function). */
|
|
if (LL_ADC_IsEnabled(ADC2) == 0)
|
|
{
|
|
/* Note: Call of the functions below are commented because they are */
|
|
/* useless in this example: */
|
|
/* setting corresponding to default configuration from reset state. */
|
|
|
|
/* Set ADC group injected trigger source */
|
|
// LL_ADC_INJ_SetTriggerSource(ADC2, LL_ADC_INJ_TRIG_SOFTWARE);
|
|
|
|
/* Set ADC group injected trigger polarity */
|
|
// LL_ADC_INJ_SetTriggerEdge(ADC2, LL_ADC_INJ_TRIG_EXT_RISING);
|
|
|
|
/* Set ADC group injected conversion trigger */
|
|
// LL_ADC_INJ_SetTrigAuto(ADC2, LL_ADC_INJ_TRIG_INDEPENDENT);
|
|
|
|
/* Set ADC group injected sequencer */
|
|
/* Note: On this STM32 serie, ADC group injected sequencer is */
|
|
/* fully configurable: sequencer length and each rank */
|
|
/* affectation to a channel are configurable. */
|
|
/* Refer to description of function */
|
|
/* "LL_ADC_INJ_SetSequencerLength()". */
|
|
|
|
/* Set ADC group injected sequencer length and scan direction */
|
|
// LL_ADC_INJ_SetSequencerLength(ADC2, LL_ADC_INJ_SEQ_SCAN_DISABLE);
|
|
|
|
/* Set ADC group injected sequencer discontinuous mode */
|
|
// LL_ADC_INJ_SetSequencerDiscont(ADC2, LL_ADC_INJ_SEQ_DISCONT_DISABLE);
|
|
|
|
/* Set ADC group injected sequence: channel on the selected sequence rank. */
|
|
// LL_ADC_INJ_SetSequencerRanks(ADC2, LL_ADC_INJ_RANK_1, LL_ADC_CHANNEL_4);
|
|
}
|
|
|
|
|
|
/*## Configuration of ADC hierarchical scope: channels #####################*/
|
|
/* Note: not configured: In this example, ADC slave group regular converts */
|
|
/* the same channel as ADC master group regular. */
|
|
/* Channel configuration same as ADC master. */
|
|
|
|
|
|
/*## Configuration of ADC transversal scope: analog watchdog ###############*/
|
|
|
|
/* Note: On this STM32 serie, there is only 1 analog watchdog available. */
|
|
|
|
/* Set ADC analog watchdog: channels to be monitored */
|
|
// LL_ADC_SetAnalogWDMonitChannels(ADC2, LL_ADC_AWD_DISABLE);
|
|
|
|
/* Set ADC analog watchdog: thresholds */
|
|
// LL_ADC_SetAnalogWDThresholds(ADC2, LL_ADC_AWD_THRESHOLD_HIGH, __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B));
|
|
// LL_ADC_SetAnalogWDThresholds(ADC2, LL_ADC_AWD_THRESHOLD_LOW, 0x000);
|
|
|
|
|
|
/*## Configuration of ADC transversal scope: oversampling ##################*/
|
|
|
|
/* Note: Feature not available on this STM32 serie */
|
|
|
|
|
|
/*## Configuration of ADC interruptions ####################################*/
|
|
/* Note: In this example, no ADC interruption enabled */
|
|
|
|
/* Note: in this example, ADC group regular end of conversions */
|
|
/* (number of ADC conversions defined by DMA buffer size) */
|
|
/* are notified by DMA transfer interruptions). */
|
|
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Perform ADC activation procedure to make it ready to convert
|
|
* (ADC instance: ADC1).
|
|
* @note Operations:
|
|
* - ADC instance
|
|
* - Run ADC self calibration
|
|
* - Enable ADC
|
|
* - ADC group regular
|
|
* none: ADC conversion start-stop to be performed
|
|
* after this function
|
|
* - ADC group injected
|
|
* none: ADC conversion start-stop to be performed
|
|
* after this function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void Activate_ADC(void)
|
|
{
|
|
__IO uint32_t wait_loop_index = 0;
|
|
#if (USE_TIMEOUT == 1)
|
|
uint32_t Timeout = 0; /* Variable used for timeout management */
|
|
#endif /* USE_TIMEOUT */
|
|
|
|
/*## Operation on ADC hierarchical scope: ADC instance #####################*/
|
|
|
|
/* Note: Hardware constraint (refer to description of the functions */
|
|
/* below): */
|
|
/* On this STM32 serie, setting of these features are not */
|
|
/* conditioned to ADC state. */
|
|
/* However, in order to be compliant with other STM32 series */
|
|
/* and to show the best practice usages, ADC state is checked. */
|
|
/* Software can be optimized by removing some of these checks, if */
|
|
/* they are not relevant considering previous settings and actions */
|
|
/* in user application. */
|
|
if (LL_ADC_IsEnabled(ADC1) == 0)
|
|
{
|
|
/* Enable ADC */
|
|
LL_ADC_Enable(ADC1);
|
|
|
|
/* Delay between ADC enable and ADC start of calibration. */
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles (depends on compilation optimization). */
|
|
wait_loop_index = (ADC_DELAY_ENABLE_CALIB_CPU_CYCLES >> 1);
|
|
while(wait_loop_index != 0)
|
|
{
|
|
wait_loop_index--;
|
|
}
|
|
|
|
/* Run ADC self calibration */
|
|
LL_ADC_StartCalibration(ADC1);
|
|
|
|
/* Poll for ADC effectively calibrated */
|
|
#if (USE_TIMEOUT == 1)
|
|
Timeout = ADC_CALIBRATION_TIMEOUT_MS;
|
|
#endif /* USE_TIMEOUT */
|
|
|
|
while (LL_ADC_IsCalibrationOnGoing(ADC1) != 0)
|
|
{
|
|
#if (USE_TIMEOUT == 1)
|
|
/* Check Systick counter flag to decrement the time-out value */
|
|
if (LL_SYSTICK_IsActiveCounterFlag())
|
|
{
|
|
if(Timeout-- == 0)
|
|
{
|
|
/* Time-out occurred. Set LED to blinking mode */
|
|
LED_Blinking(LED_BLINK_ERROR);
|
|
}
|
|
}
|
|
#endif /* USE_TIMEOUT */
|
|
}
|
|
|
|
}
|
|
|
|
/*## Operation on ADC hierarchical scope: ADC group regular ################*/
|
|
/* Note: No operation on ADC group regular performed here. */
|
|
/* ADC group regular conversions to be performed after this function */
|
|
/* using function: */
|
|
/* "LL_ADC_REG_StartConversion();" */
|
|
|
|
/*## Operation on ADC hierarchical scope: ADC group injected ###############*/
|
|
/* Note: No operation on ADC group injected performed here. */
|
|
/* ADC group injected conversions to be performed after this function */
|
|
/* using function: */
|
|
/* "LL_ADC_INJ_StartConversion();" */
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Perform ADC activation procedure to make it ready to convert
|
|
* (ADC instance: ADC2, used as ADC slave in multimode configuration).
|
|
* @note Operations:
|
|
* - ADC instance
|
|
* - Run ADC self calibration
|
|
* - Enable ADC
|
|
* - ADC group regular
|
|
* none: ADC conversion start-stop to be performed
|
|
* after this function
|
|
* - ADC group injected
|
|
* none: ADC conversion start-stop to be performed
|
|
* after this function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void Activate_ADC_slave(void)
|
|
{
|
|
__IO uint32_t wait_loop_index = 0;
|
|
#if (USE_TIMEOUT == 1)
|
|
uint32_t Timeout = 0; /* Variable used for timeout management */
|
|
#endif /* USE_TIMEOUT */
|
|
|
|
/*## Operation on ADC hierarchical scope: ADC instance #####################*/
|
|
|
|
/* Note: Hardware constraint (refer to description of the functions */
|
|
/* below): */
|
|
/* On this STM32 serie, setting of these features are not */
|
|
/* conditioned to ADC state. */
|
|
/* However, in order to be compliant with other STM32 series */
|
|
/* and to show the best practice usages, ADC state is checked. */
|
|
/* Software can be optimized by removing some of these checks, if */
|
|
/* they are not relevant considering previous settings and actions */
|
|
/* in user application. */
|
|
if (LL_ADC_IsEnabled(ADC2) == 0)
|
|
{
|
|
/* Enable ADC */
|
|
LL_ADC_Enable(ADC2);
|
|
|
|
/* Delay between ADC enable and ADC start of calibration. */
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles (depends on compilation optimization). */
|
|
wait_loop_index = (ADC_DELAY_ENABLE_CALIB_CPU_CYCLES >> 1);
|
|
while(wait_loop_index != 0)
|
|
{
|
|
wait_loop_index--;
|
|
}
|
|
|
|
/* Run ADC self calibration */
|
|
LL_ADC_StartCalibration(ADC2);
|
|
|
|
/* Poll for ADC effectively calibrated */
|
|
#if (USE_TIMEOUT == 1)
|
|
Timeout = ADC_CALIBRATION_TIMEOUT_MS;
|
|
#endif /* USE_TIMEOUT */
|
|
|
|
while (LL_ADC_IsCalibrationOnGoing(ADC2) != 0)
|
|
{
|
|
#if (USE_TIMEOUT == 1)
|
|
/* Check Systick counter flag to decrement the time-out value */
|
|
if (LL_SYSTICK_IsActiveCounterFlag())
|
|
{
|
|
if(Timeout-- == 0)
|
|
{
|
|
/* Time-out occurred. Set LED to blinking mode */
|
|
LED_Blinking(LED_BLINK_ERROR);
|
|
}
|
|
}
|
|
#endif /* USE_TIMEOUT */
|
|
}
|
|
|
|
}
|
|
|
|
/*## Operation on ADC hierarchical scope: ADC group regular ################*/
|
|
/* Note: No operation on ADC group regular performed here. */
|
|
/* In ADC multimode group regular interleaved, ADC slave conversions */
|
|
/* start and stop are controlled by ADC master. */
|
|
|
|
/*## Operation on ADC hierarchical scope: ADC group injected ###############*/
|
|
/* Note: No operation on ADC group injected performed here. */
|
|
/* ADC group injected conversions to be performed after this function */
|
|
/* using function: */
|
|
/* "LL_ADC_INJ_StartConversion();" */
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Initialize LED2.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void LED_Init(void)
|
|
{
|
|
/* Enable the LED2 Clock */
|
|
LED2_GPIO_CLK_ENABLE();
|
|
|
|
/* Configure IO in output push-pull mode to drive external LED2 */
|
|
LL_GPIO_SetPinMode(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_MODE_OUTPUT);
|
|
/* Reset value is LL_GPIO_OUTPUT_PUSHPULL */
|
|
//LL_GPIO_SetPinOutputType(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_OUTPUT_PUSHPULL);
|
|
/* Reset value is LL_GPIO_SPEED_FREQ_LOW */
|
|
//LL_GPIO_SetPinSpeed(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_SPEED_FREQ_LOW);
|
|
/* Reset value is LL_GPIO_PULL_DOWN */
|
|
//LL_GPIO_SetPinPull(LED2_GPIO_PORT, LED2_PIN, LL_GPIO_PULL_DOWN);
|
|
}
|
|
|
|
/**
|
|
* @brief Turn-on LED2.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void LED_On(void)
|
|
{
|
|
/* Turn LED2 on */
|
|
LL_GPIO_SetOutputPin(LED2_GPIO_PORT, LED2_PIN);
|
|
}
|
|
|
|
/**
|
|
* @brief Turn-off LED2.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void LED_Off(void)
|
|
{
|
|
/* Turn LED2 off */
|
|
LL_GPIO_ResetOutputPin(LED2_GPIO_PORT, LED2_PIN);
|
|
}
|
|
|
|
/**
|
|
* @brief Set LED2 to Blinking mode for an infinite loop (toggle period based on value provided as input parameter).
|
|
* @param Period : Period of time (in ms) between each toggling of LED
|
|
* This parameter can be user defined values. Pre-defined values used in that example are :
|
|
* @arg LED_BLINK_FAST : Fast Blinking
|
|
* @arg LED_BLINK_SLOW : Slow Blinking
|
|
* @arg LED_BLINK_ERROR : Error specific Blinking
|
|
* @retval None
|
|
*/
|
|
void LED_Blinking(uint32_t Period)
|
|
{
|
|
/* Turn LED2 on */
|
|
LL_GPIO_SetOutputPin(LED2_GPIO_PORT, LED2_PIN);
|
|
|
|
/* Toggle IO in an infinite loop */
|
|
while (1)
|
|
{
|
|
LL_GPIO_TogglePin(LED2_GPIO_PORT, LED2_PIN);
|
|
LL_mDelay(Period);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Configures User push-button in EXTI Line Mode.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void UserButton_Init(void)
|
|
{
|
|
/* Enable the BUTTON Clock */
|
|
USER_BUTTON_GPIO_CLK_ENABLE();
|
|
|
|
/* Configure GPIO for BUTTON */
|
|
LL_GPIO_SetPinMode(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_MODE_INPUT);
|
|
LL_GPIO_SetPinPull(USER_BUTTON_GPIO_PORT, USER_BUTTON_PIN, LL_GPIO_PULL_DOWN);
|
|
|
|
/* if(Button_Mode == BUTTON_MODE_EXTI) */
|
|
{
|
|
/* Connect External Line to the GPIO */
|
|
USER_BUTTON_SYSCFG_SET_EXTI();
|
|
|
|
/* Enable a rising trigger EXTI line 13 Interrupt */
|
|
USER_BUTTON_EXTI_LINE_ENABLE();
|
|
USER_BUTTON_EXTI_FALLING_TRIG_ENABLE();
|
|
|
|
/* Configure NVIC for USER_BUTTON_EXTI_IRQn */
|
|
NVIC_EnableIRQ(USER_BUTTON_EXTI_IRQn);
|
|
NVIC_SetPriority(USER_BUTTON_EXTI_IRQn,0x03);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* The system Clock is configured as follow :
|
|
* System Clock source = PLL (HSE)
|
|
* SYSCLK(Hz) = 72000000
|
|
* HCLK(Hz) = 72000000
|
|
* AHB Prescaler = 1
|
|
* APB1 Prescaler = 2
|
|
* APB2 Prescaler = 1
|
|
* HSE Frequency(Hz) = 8000000
|
|
* PLLMUL = 9
|
|
* Flash Latency(WS) = 2
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
/* Set FLASH latency */
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
|
|
|
|
/* Enable HSE oscillator */
|
|
LL_RCC_HSE_EnableBypass();
|
|
LL_RCC_HSE_Enable();
|
|
while(LL_RCC_HSE_IsReady() != 1)
|
|
{
|
|
};
|
|
|
|
/* Main PLL configuration and activation */
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE_DIV_1, LL_RCC_PLL_MUL_9);
|
|
|
|
LL_RCC_PLL_Enable();
|
|
while(LL_RCC_PLL_IsReady() != 1)
|
|
{
|
|
};
|
|
|
|
/* Sysclk activation on the main PLL */
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
{
|
|
};
|
|
|
|
/* Set APB1 & APB2 prescaler*/
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
|
|
/* Set systick to 1ms in using frequency set to 72MHz */
|
|
LL_Init1msTick(72000000);
|
|
|
|
/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
|
|
LL_SetSystemCoreClock(72000000);
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/* USER IRQ HANDLER TREATMENT */
|
|
/******************************************************************************/
|
|
|
|
/**
|
|
* @brief Function to manage IRQ Handler
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void UserButton_Callback(void)
|
|
{
|
|
/* Start ADC conversion only on the first press on push button */
|
|
if (ubDmaTransferStatus == 2)
|
|
{
|
|
/* Update status variable of DMA transfer */
|
|
ubDmaTransferStatus = 0;
|
|
|
|
/* Start ADC group regular conversion */
|
|
/* Note: Hardware constraint (refer to description of the functions */
|
|
/* below): */
|
|
/* On this STM32 serie, setting of these features are not */
|
|
/* conditioned to ADC state. */
|
|
/* However, in order to be compliant with other STM32 series */
|
|
/* and to show the best practice usages, ADC state is checked. */
|
|
/* Software can be optimized by removing some of these checks, if */
|
|
/* they are not relevant considering previous settings and actions */
|
|
/* in user application. */
|
|
if (LL_ADC_IsEnabled(ADC1) == 1)
|
|
{
|
|
LL_ADC_REG_StartConversionExtTrig(ADC2, LL_ADC_REG_TRIG_EXT_RISING);
|
|
LL_ADC_REG_StartConversionSWStart(ADC1);
|
|
}
|
|
else
|
|
{
|
|
/* Error: ADC conversion start could not be performed */
|
|
LED_Blinking(LED_BLINK_ERROR);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief DMA transfer complete callback
|
|
* @note This function is executed when the transfer complete interrupt
|
|
* is generated
|
|
* @retval None
|
|
*/
|
|
void AdcDmaTransferComplete_Callback()
|
|
{
|
|
uint32_t tmp_index = 0;
|
|
|
|
/* For the purpose of this example, dispatch multimode dual conversion data */
|
|
/* into arrays corresponding to ADC master and ADC slave conversion data. */
|
|
/* Note: On this STM32 device, in multimode, ADC conversion data are */
|
|
/* ADC master and ADC slave conversion data concatenated in the */
|
|
/* same register. There is no other alternative have conversion data */
|
|
/* of ADC master and ADC slave dispatched directly. */
|
|
/* Management of the 2nd half of the buffer */
|
|
for (tmp_index = (ADC_CONVERTED_DATA_BUFFER_SIZE/2); tmp_index < ADC_CONVERTED_DATA_BUFFER_SIZE; tmp_index++)
|
|
{
|
|
aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);
|
|
aADCyMultimodeDualSlaveConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
|
|
}
|
|
|
|
/* Update status variable of DMA transfer */
|
|
ubDmaTransferStatus = 1;
|
|
|
|
/* Set LED depending on DMA transfer status */
|
|
/* - Turn-on if DMA transfer is completed */
|
|
/* - Turn-off if DMA transfer is not completed */
|
|
LED_On();
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief DMA half transfer callback
|
|
* @note This function is executed when the half transfer interrupt
|
|
* is generated
|
|
* @retval None
|
|
*/
|
|
void AdcDmaTransferHalf_Callback()
|
|
{
|
|
uint32_t tmp_index = 0;
|
|
|
|
/* For the purpose of this example, dispatch multimode dual conversion data */
|
|
/* into arrays corresponding to ADC master and ADC slave conversion data. */
|
|
/* Note: On this STM32 device, in multimode, ADC conversion data are */
|
|
/* ADC master and ADC slave conversion data concatenated in the */
|
|
/* same register. There is no other alternative have conversion data */
|
|
/* of ADC master and ADC slave dispatched directly. */
|
|
/* Management of the 1st half of the buffer */
|
|
for (tmp_index = 0; tmp_index < (ADC_CONVERTED_DATA_BUFFER_SIZE/2); tmp_index++)
|
|
{
|
|
aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);
|
|
aADCyMultimodeDualSlaveConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
|
|
}
|
|
|
|
/* Update status variable of DMA transfer */
|
|
ubDmaTransferStatus = 0;
|
|
|
|
/* Set LED depending on DMA transfer status */
|
|
/* - Turn-on if DMA transfer is completed */
|
|
/* - Turn-off if DMA transfer is not completed */
|
|
LED_Off();
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief DMA transfer error callback
|
|
* @note This function is executed when the transfer error interrupt
|
|
* is generated during DMA transfer
|
|
* @retval None
|
|
*/
|
|
void AdcDmaTransferError_Callback()
|
|
{
|
|
if(ubDmaTransferStatus == 1)
|
|
{
|
|
/* Update status variable of DMA transfer */
|
|
ubDmaTransferStatus = 0;
|
|
}
|
|
|
|
/* Dummy check to avoid warning of variables unused */
|
|
if((aADCxMultimodeDualMasterConvertedData[0] != 0) ||
|
|
(aADCyMultimodeDualSlaveConvertedData[0] != 0) )
|
|
{
|
|
aADCxMultimodeDualMasterConvertedData[0] = 0;
|
|
aADCyMultimodeDualSlaveConvertedData[0] = 0;
|
|
}
|
|
|
|
/* Error detected during DMA transfer */
|
|
LED_Blinking(LED_BLINK_ERROR);
|
|
}
|
|
|
|
#ifdef USE_FULL_ASSERT
|
|
|
|
/**
|
|
* @brief Reports the name of the source file and the source line number
|
|
* where the assert_param error has occurred.
|
|
* @param file: pointer to the source file name
|
|
* @param line: assert_param error line source number
|
|
* @retval None
|
|
*/
|
|
void assert_failed(uint8_t *file, uint32_t line)
|
|
{
|
|
/* User can add his own implementation to report the file name and line number,
|
|
ex: printf("Wrong parameters value: file %s on line %d", file, line) */
|
|
|
|
/* Infinite loop */
|
|
while (1)
|
|
{
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|