96 lines
3.9 KiB
Plaintext
96 lines
3.9 KiB
Plaintext
/**
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@page TIM_BreakAndDeadtime TIM example
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@verbatim
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******************** (C) COPYRIGHT 2016 STMicroelectronics *******************
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* @file Examples_LL/TIM/TIM_BreakAndDeadtime/readme.txt
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* @author MCD Application Team
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* @brief Description of the TIM_BreakAndDeadtime example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of the TIM peripheral to
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– generate three center-aligned PWM and complementary PWM signals
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– insert a defined dead time value
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– use the break feature
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– lock the desired parameters
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This example is based on the STM32F1xx TIM LL API.
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The peripheral initialization is done using LL unitary
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services functions for optimization purpose (performance and size).
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TIM1CLK is fixed to 72 MHz, the TIM1 Prescaler is set to have
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TIM1 counter clock = 10 MHz.
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The TIM1 auto-reload is set to generate PWM signal at 10 KHz:
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The Three Duty cycles are computed as the following description:
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The channel 1 duty cycle is set to 50% so channel 1N is set to 50%.
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The channel 2 duty cycle is set to 25% so channel 2N is set to 75%.
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The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%.
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A dead time equal to 4 us is inserted between
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the different complementary signals, and the Lock level 1 is selected.
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- The OCx output signal is the same as the reference signal except for the rising edge,
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which is delayed relative to the reference rising edge.
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- The OCxN output signal is the opposite of the reference signal except for the rising
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edge, which is delayed relative to the reference falling edge
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Note that calculated duty cycles apply to the reference signal (OCxREF) from
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which outputs OCx and OCxN are generated. As dead time insertion is enabled the
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duty cycle measured on OCx will be slightly lower.
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The break Polarity is used at High level.
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The TIM1 waveforms can be displayed using an oscilloscope.
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@par Directory contents
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- TIM/TIM_BreakAndDeadtime/Inc/stm32f1xx_it.h Interrupt handlers header file
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- TIM/TIM_BreakAndDeadtime/Inc/main.h Header for main.c module
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- TIM/TIM_BreakAndDeadtime/Inc/stm32_assert.h Template file to include assert_failed function
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- TIM/TIM_BreakAndDeadtime/Src/stm32f1xx_it.c Interrupt handlers
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- TIM/TIM_BreakAndDeadtime/Src/main.c Main program
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- TIM/TIM_BreakAndDeadtime/Src/system_stm32f1xx.c STM32F1xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F103xB devices.
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- This example has been tested with STM32F103RB-Nucleo board and can be
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easily tailored to any other supported device and development board.
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- STM32F103RB-Nucleo Set-up
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- Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
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- TIM1_CH1 PA.08: connected to pin 8 of CN9 connector
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- TIM1_CH1N PB.13: connected to pin 30 of CN10 connector
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- TIM1_CH2 PA.09: connected to pin 1 of CN5 connector
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- TIM1_CH2N PB.14: connected to pin 28 of CN10 connector
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- TIM1_CH3 PA.10: connected to pin 3 of CN9 connector
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- TIM1_CH3N PB.15: connected to pin 26 of CN10 connector
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- Connect the TIM1 break to the GND. To generate a break event, switch this
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pin level from 0V to 3.3V.
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- TIM1_BKIN PB.12: connected to pin 16 of CN10 connector
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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