1376 lines
65 KiB
C
1376 lines
65 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_hal_rcc.h
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* @author MCD Application Team
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* @brief Header file of RCC HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_HAL_RCC_H
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#define __STM32F1xx_HAL_RCC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @addtogroup RCC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup RCC_Exported_Types RCC Exported Types
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* @{
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*/
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/**
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* @brief RCC PLL configuration structure definition
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*/
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typedef struct
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{
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uint32_t PLLState; /*!< PLLState: The new state of the PLL.
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This parameter can be a value of @ref RCC_PLL_Config */
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uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
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This parameter must be a value of @ref RCC_PLL_Clock_Source */
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uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
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This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
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} RCC_PLLInitTypeDef;
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/**
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* @brief RCC System, AHB and APB busses clock configuration structure definition
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*/
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typedef struct
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{
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uint32_t ClockType; /*!< The clock to be configured.
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This parameter can be a value of @ref RCC_System_Clock_Type */
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uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
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This parameter can be a value of @ref RCC_System_Clock_Source */
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uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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This parameter can be a value of @ref RCC_AHB_Clock_Source */
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uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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} RCC_ClkInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCC_Exported_Constants RCC Exported Constants
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* @{
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*/
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/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
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* @{
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*/
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#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
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#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
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/**
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* @}
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*/
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/** @defgroup RCC_Oscillator_Type Oscillator Type
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* @{
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*/
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#define RCC_OSCILLATORTYPE_NONE 0x00000000U
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#define RCC_OSCILLATORTYPE_HSE 0x00000001U
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#define RCC_OSCILLATORTYPE_HSI 0x00000002U
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#define RCC_OSCILLATORTYPE_LSE 0x00000004U
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#define RCC_OSCILLATORTYPE_LSI 0x00000008U
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/**
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* @}
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*/
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/** @defgroup RCC_HSE_Config HSE Config
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* @{
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*/
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#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
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#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
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#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
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/**
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* @}
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*/
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/** @defgroup RCC_LSE_Config LSE Config
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* @{
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*/
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#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
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#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
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#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
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/**
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* @}
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*/
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/** @defgroup RCC_HSI_Config HSI Config
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* @{
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*/
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#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
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#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
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#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
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/**
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* @}
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*/
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/** @defgroup RCC_LSI_Config LSI Config
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* @{
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*/
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#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
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#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
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/**
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* @}
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*/
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/** @defgroup RCC_PLL_Config PLL Config
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* @{
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*/
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#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
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#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
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#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
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/**
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* @}
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*/
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/** @defgroup RCC_System_Clock_Type System Clock Type
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* @{
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*/
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#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
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#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
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#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
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#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
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/**
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* @}
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*/
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/** @defgroup RCC_System_Clock_Source System Clock Source
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* @{
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*/
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#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
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#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
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#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
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/**
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* @}
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*/
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/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
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* @{
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*/
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#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
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#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
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#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
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/**
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* @}
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*/
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/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
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* @{
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*/
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#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
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#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
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#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
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#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
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#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
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#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
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#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
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#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
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#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
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/**
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* @}
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*/
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/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
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* @{
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*/
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#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
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#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
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#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
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#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
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#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
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/**
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* @}
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*/
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/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
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* @{
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*/
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#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */
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#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
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#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
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#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
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/**
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* @}
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*/
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/** @defgroup RCC_MCO_Index MCO Index
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* @{
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*/
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#define RCC_MCO1 0x00000000U
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#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
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/**
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* @}
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*/
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/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
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* @{
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*/
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#define RCC_MCODIV_1 0x00000000U
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/**
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* @}
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*/
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/** @defgroup RCC_Interrupt Interrupts
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* @{
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*/
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#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
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#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
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#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
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#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
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#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
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#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
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/**
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* @}
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*/
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/** @defgroup RCC_Flag Flags
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* Elements values convention: XXXYYYYYb
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* - YYYYY : Flag position in the register
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* - XXX : Register index
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* - 001: CR register
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* - 010: BDCR register
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* - 011: CSR register
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* @{
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*/
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/* Flags in the CR register */
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#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
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#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
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#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
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/* Flags in the CSR register */
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#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
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#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
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#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */
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#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
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#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
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#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
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#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
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/* Flags in the BDCR register */
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#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup RCC_Exported_Macros RCC Exported Macros
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* @{
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*/
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/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
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* @brief Enable or disable the AHB1 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @{
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*/
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#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_CRC_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
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#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
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#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
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#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
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/**
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* @}
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*/
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/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
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* @brief Get the enable or disable status of the AHB peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @{
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*/
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#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
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#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
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#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
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#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
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#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
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#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
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#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
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#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
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/**
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* @}
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*/
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/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
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* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @{
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*/
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#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_USART2_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_BKP_CLK_ENABLE() do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
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/* Delay after an RCC peripheral clock enabling */\
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
|
|
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
|
|
#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
|
|
#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
|
|
#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
|
|
|
|
#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
|
|
#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
|
|
* @brief Get the enable or disable status of the APB1 peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
|
|
#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
|
|
#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
|
|
#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
|
|
#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
|
|
#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
|
|
#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
|
|
#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
|
|
#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
|
|
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
|
|
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
|
|
#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
|
|
#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
|
|
#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
|
|
#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
|
|
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
|
/* Delay after an RCC peripheral clock enabling */\
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
|
|
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
|
|
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
|
|
#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
|
|
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
|
|
#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
|
|
|
|
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
|
|
#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
|
|
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
|
|
* @brief Get the enable or disable status of the APB2 peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
|
|
#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
|
|
#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
|
|
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
|
|
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
|
|
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
|
|
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
|
|
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
|
|
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
|
|
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
|
|
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
|
|
#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
|
|
#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
|
|
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
|
|
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
|
|
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
|
|
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
|
|
#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
|
|
#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
|
|
* @brief Force or release APB1 peripheral reset.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
|
|
#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
|
|
#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
|
|
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
|
|
#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
|
|
#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
|
|
|
|
#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
|
|
#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
|
|
|
|
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
|
|
#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
|
|
#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
|
|
#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
|
|
#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
|
|
#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
|
|
|
|
#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
|
|
#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
|
|
* @brief Force or release APB2 peripheral reset.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
|
|
#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
|
|
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
|
|
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
|
|
#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
|
|
#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
|
|
#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
|
|
|
|
#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
|
|
#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
|
|
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
|
|
|
|
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
|
|
#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
|
|
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
|
|
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
|
|
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
|
|
#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
|
|
#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
|
|
|
|
#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
|
|
#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
|
|
#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_HSI_Configuration HSI Configuration
|
|
* @{
|
|
*/
|
|
|
|
/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
|
|
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
|
|
* @note HSI can not be stopped if it is used as system clock source. In this case,
|
|
* you have to select another source of the system clock then stop the HSI.
|
|
* @note After enabling the HSI, the application software should wait on HSIRDY
|
|
* flag to be set indicating that HSI clock is stable and can be used as
|
|
* system clock source.
|
|
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
|
|
* clock cycles.
|
|
*/
|
|
#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
|
|
#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
|
|
|
|
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
|
|
* @note The calibration is used to compensate for the variations in voltage
|
|
* and temperature that influence the frequency of the internal HSI RC.
|
|
* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
|
|
* (default is RCC_HSICALIBRATION_DEFAULT).
|
|
* This parameter must be a number between 0 and 0x1F.
|
|
*/
|
|
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
|
|
(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_LSI_Configuration LSI Configuration
|
|
* @{
|
|
*/
|
|
|
|
/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
|
|
* @note After enabling the LSI, the application software should wait on
|
|
* LSIRDY flag to be set indicating that LSI clock is stable and can
|
|
* be used to clock the IWDG and/or the RTC.
|
|
*/
|
|
#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
|
|
|
|
/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
|
|
* @note LSI can not be disabled if the IWDG is running.
|
|
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
|
|
* clock cycles.
|
|
*/
|
|
#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_HSE_Configuration HSE Configuration
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Macro to configure the External High Speed oscillator (HSE).
|
|
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
|
|
* software should wait on HSERDY flag to be set indicating that HSE clock
|
|
* is stable and can be used to clock the PLL and/or system clock.
|
|
* @note HSE state can not be changed if it is used directly or through the
|
|
* PLL as system clock. In this case, you have to select another source
|
|
* of the system clock then change the HSE state (ex. disable it).
|
|
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
|
|
* @note This function reset the CSSON bit, so if the clock security system(CSS)
|
|
* was previously enabled you have to enable it again after calling this
|
|
* function.
|
|
* @param __STATE__ specifies the new state of the HSE.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
|
|
* 6 HSE oscillator clock cycles.
|
|
* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
|
|
* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
|
|
*/
|
|
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
|
|
do{ \
|
|
if ((__STATE__) == RCC_HSE_ON) \
|
|
{ \
|
|
SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
} \
|
|
else if ((__STATE__) == RCC_HSE_OFF) \
|
|
{ \
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
} \
|
|
else if ((__STATE__) == RCC_HSE_BYPASS) \
|
|
{ \
|
|
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
} \
|
|
else \
|
|
{ \
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
} \
|
|
}while(0U)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_LSE_Configuration LSE Configuration
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Macro to configure the External Low Speed oscillator (LSE).
|
|
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
|
|
* @note As the LSE is in the Backup domain and write access is denied to
|
|
* this domain after reset, you have to enable write access using
|
|
* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
|
* (to be done once after reset).
|
|
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
|
|
* software should wait on LSERDY flag to be set indicating that LSE clock
|
|
* is stable and can be used to clock the RTC.
|
|
* @param __STATE__ specifies the new state of the LSE.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
|
|
* 6 LSE oscillator clock cycles.
|
|
* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
|
|
* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
|
|
*/
|
|
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
|
|
do{ \
|
|
if ((__STATE__) == RCC_LSE_ON) \
|
|
{ \
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
} \
|
|
else if ((__STATE__) == RCC_LSE_OFF) \
|
|
{ \
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
} \
|
|
else if ((__STATE__) == RCC_LSE_BYPASS) \
|
|
{ \
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
} \
|
|
else \
|
|
{ \
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
} \
|
|
}while(0U)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_PLL_Configuration PLL Configuration
|
|
* @{
|
|
*/
|
|
|
|
/** @brief Macro to enable the main PLL.
|
|
* @note After enabling the main PLL, the application software should wait on
|
|
* PLLRDY flag to be set indicating that PLL clock is stable and can
|
|
* be used as system clock source.
|
|
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
|
|
*/
|
|
#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
|
|
|
|
/** @brief Macro to disable the main PLL.
|
|
* @note The main PLL can not be disabled if it is used as system clock source
|
|
*/
|
|
#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
|
|
|
|
/** @brief Macro to configure the main PLL clock source and multiplication factors.
|
|
* @note This function must be used only when the main PLL is disabled.
|
|
*
|
|
* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
|
|
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
|
|
* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
|
|
* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
|
|
@if STM32F105xC
|
|
* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
|
|
@elseif STM32F107xC
|
|
* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
|
|
@else
|
|
* @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
|
|
* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
|
|
* @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
|
|
* @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
|
|
* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
|
|
* @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
|
|
* @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
|
|
* @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
|
|
* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
|
|
@endif
|
|
* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
|
|
* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
|
|
*
|
|
*/
|
|
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
|
|
MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
|
|
|
|
/** @brief Get oscillator clock selected as PLL input clock
|
|
* @retval The clock source used for PLL entry. The returned value can be one
|
|
* of the following:
|
|
* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
|
|
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
|
|
*/
|
|
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Get_Clock_source Get Clock source
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Macro to configure the system clock source.
|
|
* @param __SYSCLKSOURCE__ specifies the system clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
|
|
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
|
|
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
|
|
*/
|
|
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
|
|
|
|
/** @brief Macro to get the clock source used as system clock.
|
|
* @retval The clock source used as system clock. The returned value can be one
|
|
* of the following:
|
|
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
|
|
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
|
|
* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
|
|
*/
|
|
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
|
|
* @{
|
|
*/
|
|
|
|
#if defined(RCC_CFGR_MCO_3)
|
|
/** @brief Macro to configure the MCO clock.
|
|
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
|
|
* @param __MCODIV__ specifies the MCO clock prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
|
|
*/
|
|
#else
|
|
/** @brief Macro to configure the MCO clock.
|
|
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
|
|
* @param __MCODIV__ specifies the MCO clock prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
|
|
*/
|
|
#endif
|
|
|
|
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
|
|
* @{
|
|
*/
|
|
|
|
/** @brief Macro to configure the RTC clock (RTCCLK).
|
|
* @note As the RTC clock configuration bits are in the Backup domain and write
|
|
* access is denied to this domain after reset, you have to enable write
|
|
* access using the Power Backup Access macro before to configure
|
|
* the RTC clock source (to be done once after reset).
|
|
* @note Once the RTC clock is configured it can't be changed unless the
|
|
* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
|
|
* a Power On Reset (POR).
|
|
*
|
|
* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
|
|
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
|
|
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
|
|
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
|
|
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
|
* work in STOP and STANDBY modes, and can be used as wakeup source.
|
|
* However, when the HSE clock is used as RTC clock source, the RTC
|
|
* cannot be used in STOP and STANDBY modes.
|
|
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
|
|
* RTC clock source).
|
|
*/
|
|
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
|
|
|
|
/** @brief Macro to get the RTC clock source.
|
|
* @retval The clock source can be one of the following values:
|
|
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
|
|
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
|
|
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
|
|
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
|
|
*/
|
|
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
|
|
|
|
/** @brief Macro to enable the the RTC clock.
|
|
* @note These macros must be used only after the RTC clock source was selected.
|
|
*/
|
|
#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
|
|
|
|
/** @brief Macro to disable the the RTC clock.
|
|
* @note These macros must be used only after the RTC clock source was selected.
|
|
*/
|
|
#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
|
|
|
|
/** @brief Macro to force the Backup domain reset.
|
|
* @note This function resets the RTC peripheral (including the backup registers)
|
|
* and the RTC clock source selection in RCC_BDCR register.
|
|
*/
|
|
#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
|
|
|
|
/** @brief Macros to release the Backup domain reset.
|
|
*/
|
|
#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
|
|
* @brief macros to manage the specified RCC Flags and interrupts.
|
|
* @{
|
|
*/
|
|
|
|
/** @brief Enable RCC interrupt.
|
|
* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
|
|
@if STM32F105xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@elsif STM32F107xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@endif
|
|
*/
|
|
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
|
|
|
|
/** @brief Disable RCC interrupt.
|
|
* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
|
|
@if STM32F105xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@elsif STM32F107xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@endif
|
|
*/
|
|
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
|
|
|
|
/** @brief Clear the RCC's interrupt pending bits.
|
|
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
|
|
* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
|
|
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
|
|
* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
|
|
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
|
|
@if STM32F105xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@elsif STM32F107xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@endif
|
|
* @arg @ref RCC_IT_CSS Clock Security System interrupt
|
|
*/
|
|
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
|
|
|
|
/** @brief Check the RCC's interrupt has occurred or not.
|
|
* @param __INTERRUPT__ specifies the RCC interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
|
|
* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
|
|
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
|
|
* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
|
|
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
|
|
@if STM32F105xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@elsif STM32F107xx
|
|
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
@endif
|
|
* @arg @ref RCC_IT_CSS Clock Security System interrupt
|
|
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
|
|
/** @brief Set RMVF bit to clear the reset flags.
|
|
* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
|
|
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
|
|
*/
|
|
#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
|
|
|
|
/** @brief Check RCC flag is set or not.
|
|
* @param __FLAG__ specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
|
|
* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
|
|
* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
|
|
@if STM32F105xx
|
|
* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
|
|
* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
|
|
@elsif STM32F107xx
|
|
* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
|
|
* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
|
|
@endif
|
|
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
|
|
* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
|
|
* @arg @ref RCC_FLAG_PINRST Pin reset.
|
|
* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
|
|
* @arg @ref RCC_FLAG_SFTRST Software reset.
|
|
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
|
|
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
|
|
* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
|
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
|
|
((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
|
|
RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Include RCC HAL Extension module */
|
|
#include "stm32f1xx_hal_rcc_ex.h"
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/** @addtogroup RCC_Exported_Functions
|
|
* @{
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*/
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/** @addtogroup RCC_Exported_Functions_Group1
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* @{
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*/
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/* Initialization and de-initialization functions ******************************/
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HAL_StatusTypeDef HAL_RCC_DeInit(void);
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HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
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HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
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/**
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* @}
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*/
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/** @addtogroup RCC_Exported_Functions_Group2
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* @{
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*/
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/* Peripheral Control functions ************************************************/
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void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
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void HAL_RCC_EnableCSS(void);
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void HAL_RCC_DisableCSS(void);
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uint32_t HAL_RCC_GetSysClockFreq(void);
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uint32_t HAL_RCC_GetHCLKFreq(void);
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uint32_t HAL_RCC_GetPCLK1Freq(void);
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uint32_t HAL_RCC_GetPCLK2Freq(void);
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void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
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void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
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/* CSS NMI IRQ handler */
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void HAL_RCC_NMI_IRQHandler(void);
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/* User Callbacks in non blocking mode (IT mode) */
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void HAL_RCC_CSSCallback(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @addtogroup RCC_Private_Constants
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* @{
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*/
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/** @defgroup RCC_Timeout RCC Timeout
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* @{
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*/
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/* Disable Backup domain write protection state change timeout */
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#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
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/* LSE state change timeout */
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#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
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#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
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#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
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#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
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#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
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#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
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/**
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* @}
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*/
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/** @defgroup RCC_Register_Offset Register offsets
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* @{
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*/
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#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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#define RCC_CR_OFFSET 0x00U
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#define RCC_CFGR_OFFSET 0x04U
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#define RCC_CIR_OFFSET 0x08U
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#define RCC_BDCR_OFFSET 0x20U
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#define RCC_CSR_OFFSET 0x24U
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/**
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* @}
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*/
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/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
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* @brief RCC registers bit address in the alias region
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* @{
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*/
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#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
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#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
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#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
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#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
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#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
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/* --- CR Register ---*/
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/* Alias word address of HSION bit */
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#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
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#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
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/* Alias word address of HSEON bit */
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#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
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#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
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/* Alias word address of CSSON bit */
|
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#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
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|
#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
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|
/* Alias word address of PLLON bit */
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|
#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
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|
#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
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|
|
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/* --- CSR Register ---*/
|
|
/* Alias word address of LSION bit */
|
|
#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
|
|
#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
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|
|
|
/* Alias word address of RMVF bit */
|
|
#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
|
|
#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
|
|
|
|
/* --- BDCR Registers ---*/
|
|
/* Alias word address of LSEON bit */
|
|
#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
|
|
#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
|
|
|
|
/* Alias word address of LSEON bit */
|
|
#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
|
|
#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
|
|
|
|
/* Alias word address of RTCEN bit */
|
|
#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
|
|
#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
|
|
|
|
/* Alias word address of BDRST bit */
|
|
#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
|
|
#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* CR register byte 2 (Bits[23:16]) base address */
|
|
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
|
|
|
|
/* CIR register byte 1 (Bits[15:8]) base address */
|
|
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
|
|
|
|
/* CIR register byte 2 (Bits[23:16]) base address */
|
|
#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
|
|
|
|
/* Defines used for Flags */
|
|
#define CR_REG_INDEX ((uint8_t)1)
|
|
#define BDCR_REG_INDEX ((uint8_t)2)
|
|
#define CSR_REG_INDEX ((uint8_t)3)
|
|
|
|
#define RCC_FLAG_MASK ((uint8_t)0x1F)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup RCC_Private_Macros
|
|
* @{
|
|
*/
|
|
/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
|
|
#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
|
|
#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
|
|
#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
|
|
((__SOURCE__) == RCC_PLLSOURCE_HSE))
|
|
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
|
|
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
|
|
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
|
|
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
|
|
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
|
|
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
|
|
((__HSE__) == RCC_HSE_BYPASS))
|
|
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
|
|
((__LSE__) == RCC_LSE_BYPASS))
|
|
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
|
|
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
|
|
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
|
|
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
|
|
((__PLL__) == RCC_PLL_ON))
|
|
|
|
#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
|
|
(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
|
|
(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
|
|
(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
|
|
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
|
|
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
|
|
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
|
|
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
|
|
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
|
|
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
|
|
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
|
|
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
|
|
((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
|
|
((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
|
|
((__HCLK__) == RCC_SYSCLK_DIV512))
|
|
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
|
|
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
|
|
((__PCLK__) == RCC_HCLK_DIV16))
|
|
#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
|
|
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
|
|
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
|
|
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
|
|
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
|
|
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32F1xx_HAL_RCC_H */
|
|
|
|
|