1001 lines
51 KiB
C
1001 lines
51 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_hal_adc.h
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* @author MCD Application Team
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* @brief Header file containing functions prototypes of ADC HAL library.
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******************************************************************************
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* @attention
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*
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_HAL_ADC_H
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#define __STM32F1xx_HAL_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @addtogroup ADC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup ADC_Exported_Types ADC Exported Types
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* @{
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*/
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/**
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* @brief Structure definition of ADC and regular group initialization
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* @note Parameters of this structure are shared within 2 scopes:
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* - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
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* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
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* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
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* ADC can be either disabled or enabled without conversion on going on regular group.
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*/
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typedef struct
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{
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uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
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or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
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This parameter can be a value of @ref ADC_Data_align */
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uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
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This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
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If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
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Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
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If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
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Scan direction is upward: from rank1 to rank 'n'.
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This parameter can be a value of @ref ADC_Scan_mode
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Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
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or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
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the last conversion of the sequence. All previous conversions would be overwritten by the last one.
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Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
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FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
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after the selected trigger occurred (software start or external trigger).
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
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To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
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This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
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FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
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Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
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Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
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If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
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This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
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uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
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If set to ADC_SOFTWARE_START, external triggers are disabled.
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If set to external trigger source, triggering is on event rising edge.
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This parameter can be a value of @ref ADC_External_trigger_source_Regular */
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}ADC_InitTypeDef;
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/**
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* @brief Structure definition of ADC channel for regular group
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* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
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* ADC can be either disabled or enabled without conversion on going on regular group.
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*/
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typedef struct
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{
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uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
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This parameter can be a value of @ref ADC_channels
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Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
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Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
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Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
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It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
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Refer to errata sheet of these devices for more details. */
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uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
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This parameter can be a value of @ref ADC_regular_rank
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Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
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uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
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Unit: ADC clock cycles
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Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
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This parameter can be a value of @ref ADC_sampling_times
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Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
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If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
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Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
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sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
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Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
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}ADC_ChannelConfTypeDef;
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/**
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* @brief ADC Configuration analog watchdog definition
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* @note The setting of these parameters with function is conditioned to ADC state.
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* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
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*/
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typedef struct
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{
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uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
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This parameter can be a value of @ref ADC_analog_watchdog_mode. */
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uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
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This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
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This parameter can be a value of @ref ADC_channels. */
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FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
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uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
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uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
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}ADC_AnalogWDGConfTypeDef;
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/**
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* @brief HAL ADC state machine: ADC states definition (bitfields)
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*/
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/* States of ADC global scope */
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#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
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#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
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#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
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#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
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/* States of ADC errors */
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#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
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#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
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#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
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/* States of ADC group regular */
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#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
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external trigger, low power auto power-on, multimode ADC master control) */
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#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
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#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
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#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */
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/* States of ADC group injected */
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#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
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external trigger, low power auto power-on, multimode ADC master control) */
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#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
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#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
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/* States of ADC analog watchdogs */
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#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
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#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
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#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
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/* States of ADC multi-mode */
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#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
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/**
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* @brief ADC handle Structure definition
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*/
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typedef struct __ADC_HandleTypeDef
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{
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ADC_TypeDef *Instance; /*!< Register base address */
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ADC_InitTypeDef Init; /*!< ADC required parameters */
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DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
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HAL_LockTypeDef Lock; /*!< ADC locking object */
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__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
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__IO uint32_t ErrorCode; /*!< ADC Error code */
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#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
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void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
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void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
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void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
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void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
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void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */
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void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
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void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
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#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
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}ADC_HandleTypeDef;
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#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
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/**
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* @brief HAL ADC Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
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HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
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HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
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HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
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HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
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HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
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HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
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} HAL_ADC_CallbackIDTypeDef;
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/**
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* @brief HAL ADC Callback pointer definition
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*/
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typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
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#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup ADC_Exported_Constants ADC Exported Constants
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* @{
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*/
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/** @defgroup ADC_Error_Code ADC Error Code
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* @{
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*/
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#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
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#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
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enable/disable, erroneous state */
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#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
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#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
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#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
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#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
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#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/** @defgroup ADC_Data_align ADC data alignment
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* @{
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*/
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#define ADC_DATAALIGN_RIGHT 0x00000000U
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#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
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/**
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* @}
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*/
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/** @defgroup ADC_Scan_mode ADC scan mode
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* @{
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*/
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/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
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/* compatibility with other STM32 devices having a sequencer with */
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/* additional options. */
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#define ADC_SCAN_DISABLE 0x00000000U
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#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
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/**
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* @}
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*/
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/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
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* @{
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*/
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#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
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#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
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/**
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* @}
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*/
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/** @defgroup ADC_channels ADC channels
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* @{
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*/
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/* Note: Depending on devices, some channels may not be available on package */
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/* pins. Refer to device datasheet for channels availability. */
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#define ADC_CHANNEL_0 0x00000000U
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#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
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#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
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#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
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#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
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#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
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#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
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#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
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#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
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#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
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#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
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#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
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/**
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* @}
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*/
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/** @defgroup ADC_sampling_times ADC sampling times
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* @{
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*/
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#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
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#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
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#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */
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#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
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#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */
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#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
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#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */
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#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
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/**
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* @}
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*/
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/** @defgroup ADC_regular_rank ADC rank into regular group
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* @{
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*/
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#define ADC_REGULAR_RANK_1 0x00000001U
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#define ADC_REGULAR_RANK_2 0x00000002U
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#define ADC_REGULAR_RANK_3 0x00000003U
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#define ADC_REGULAR_RANK_4 0x00000004U
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#define ADC_REGULAR_RANK_5 0x00000005U
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#define ADC_REGULAR_RANK_6 0x00000006U
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#define ADC_REGULAR_RANK_7 0x00000007U
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#define ADC_REGULAR_RANK_8 0x00000008U
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#define ADC_REGULAR_RANK_9 0x00000009U
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#define ADC_REGULAR_RANK_10 0x0000000AU
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#define ADC_REGULAR_RANK_11 0x0000000BU
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#define ADC_REGULAR_RANK_12 0x0000000CU
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#define ADC_REGULAR_RANK_13 0x0000000DU
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#define ADC_REGULAR_RANK_14 0x0000000EU
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#define ADC_REGULAR_RANK_15 0x0000000FU
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#define ADC_REGULAR_RANK_16 0x00000010U
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/**
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* @}
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*/
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/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
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* @{
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*/
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#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
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#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
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#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
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#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
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#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
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#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
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#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
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/**
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* @}
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*/
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/** @defgroup ADC_conversion_group ADC conversion group
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* @{
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*/
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#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
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#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
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#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_Event_type ADC Event type
|
|
* @{
|
|
*/
|
|
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
|
|
|
|
#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_interrupts_definition ADC interrupts definition
|
|
* @{
|
|
*/
|
|
#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
|
|
#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
|
|
#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_flags_definition ADC flags definition
|
|
* @{
|
|
*/
|
|
#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
|
|
#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
|
|
#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
|
|
#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
|
|
#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private constants ---------------------------------------------------------*/
|
|
|
|
/** @addtogroup ADC_Private_Constants ADC Private Constants
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup ADC_conversion_cycles ADC conversion cycles
|
|
* @{
|
|
*/
|
|
/* ADC conversion cycles (unit: ADC clock cycles) */
|
|
/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
|
|
/* resolution 12 bits) */
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
|
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
|
|
* @{
|
|
*/
|
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
|
|
(ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
|
|
ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
|
|
ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
|
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
|
|
(ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
|
|
ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
|
|
|
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
|
|
(ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
|
|
ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
|
|
ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
|
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
|
|
(ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
|
|
ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
|
|
|
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
|
|
(ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
|
|
ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
|
|
ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
|
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
|
|
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
|
|
ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
|
|
|
|
#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
|
|
#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
|
#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
|
|
#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
|
#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
|
|
#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
|
#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
|
|
#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
|
|
|
#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
|
|
#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
|
#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
|
|
#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
|
#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
|
|
#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
|
#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
|
|
#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
|
|
#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
|
|
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
|
* @{
|
|
*/
|
|
/* Macro for internal HAL driver usage, and possibly can be used into code of */
|
|
/* final user. */
|
|
|
|
/**
|
|
* @brief Enable the ADC peripheral
|
|
* @note ADC enable requires a delay for ADC stabilization time
|
|
* (refer to device datasheet, parameter tSTAB)
|
|
* @note On STM32F1, if ADC is already enabled this macro trigs a conversion
|
|
* SW start on regular group.
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_ENABLE(__HANDLE__) \
|
|
(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
|
|
|
|
/**
|
|
* @brief Disable the ADC peripheral
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_DISABLE(__HANDLE__) \
|
|
(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
|
|
|
|
/** @brief Enable the ADC end of conversion interrupt.
|
|
* @param __HANDLE__: ADC handle
|
|
* @param __INTERRUPT__: ADC Interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
|
|
* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
|
|
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
|
(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
|
|
|
|
/** @brief Disable the ADC end of conversion interrupt.
|
|
* @param __HANDLE__: ADC handle
|
|
* @param __INTERRUPT__: ADC Interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
|
|
* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
|
|
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
|
(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
|
|
|
|
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
|
|
* @param __HANDLE__: ADC handle
|
|
* @param __INTERRUPT__: ADC interrupt source to check
|
|
* This parameter can be any combination of the following values:
|
|
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
|
|
* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
|
|
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
|
(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
|
|
/** @brief Get the selected ADC's flag status.
|
|
* @param __HANDLE__: ADC handle
|
|
* @param __FLAG__: ADC flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg ADC_FLAG_STRT: ADC Regular group start flag
|
|
* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
|
|
* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
|
|
* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
|
|
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
|
|
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
|
|
|
/** @brief Clear the ADC's pending flags
|
|
* @param __HANDLE__: ADC handle
|
|
* @param __FLAG__: ADC flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg ADC_FLAG_STRT: ADC Regular group start flag
|
|
* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
|
|
* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
|
|
* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
|
|
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
|
(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
|
|
|
|
/** @brief Reset ADC handle state
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval None
|
|
*/
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
|
do{ \
|
|
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
|
|
(__HANDLE__)->MspInitCallback = NULL; \
|
|
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
} while(0)
|
|
#else
|
|
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
|
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private macro ------------------------------------------------------------*/
|
|
|
|
/** @defgroup ADC_Private_Macros ADC Private Macros
|
|
* @{
|
|
*/
|
|
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
|
/* code of final user. */
|
|
|
|
/**
|
|
* @brief Verification of ADC state: enabled or disabled
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval SET (ADC enabled) or RESET (ADC disabled)
|
|
*/
|
|
#define ADC_IS_ENABLE(__HANDLE__) \
|
|
((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
|
|
) ? SET : RESET)
|
|
|
|
/**
|
|
* @brief Test if conversion trigger of regular group is software start
|
|
* or external trigger.
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval SET (software start) or RESET (external trigger)
|
|
*/
|
|
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
|
|
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
|
|
|
|
/**
|
|
* @brief Test if conversion trigger of injected group is software start
|
|
* or external trigger.
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval SET (software start) or RESET (external trigger)
|
|
*/
|
|
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
|
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
|
|
|
|
/**
|
|
* @brief Simultaneously clears and sets specific bits of the handle State
|
|
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
|
|
* the first parameter is the ADC handle State, the second parameter is the
|
|
* bit field to clear, the third and last parameter is the bit field to set.
|
|
* @retval None
|
|
*/
|
|
#define ADC_STATE_CLR_SET MODIFY_REG
|
|
|
|
/**
|
|
* @brief Clear ADC error code (set it to error code: "no error")
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval None
|
|
*/
|
|
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
|
|
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
|
|
|
|
/**
|
|
* @brief Set ADC number of conversions into regular channel sequence length.
|
|
* @param _NbrOfConversion_: Regular channel sequence length
|
|
* @retval None
|
|
*/
|
|
#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
|
|
(((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
|
|
|
|
/**
|
|
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
|
|
* @param _SAMPLETIME_: Sample time parameter.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @retval None
|
|
*/
|
|
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
|
|
((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
|
|
|
|
/**
|
|
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
|
|
* @param _SAMPLETIME_: Sample time parameter.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @retval None
|
|
*/
|
|
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
|
|
((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
|
|
|
|
/**
|
|
* @brief Set the selected regular channel rank for rank between 1 and 6.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @param _RANKNB_: Rank number.
|
|
* @retval None
|
|
*/
|
|
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
|
|
((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
|
|
|
|
/**
|
|
* @brief Set the selected regular channel rank for rank between 7 and 12.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @param _RANKNB_: Rank number.
|
|
* @retval None
|
|
*/
|
|
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
|
|
((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
|
|
|
|
/**
|
|
* @brief Set the selected regular channel rank for rank between 13 and 16.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @param _RANKNB_: Rank number.
|
|
* @retval None
|
|
*/
|
|
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
|
|
((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
|
|
|
|
/**
|
|
* @brief Set the injected sequence length.
|
|
* @param _JSQR_JL_: Sequence length.
|
|
* @retval None
|
|
*/
|
|
#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
|
|
(((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
|
|
|
|
/**
|
|
* @brief Set the selected injected channel rank
|
|
* Note: on STM32F1 devices, channel rank position in JSQR register
|
|
* is depending on total number of ranks selected into
|
|
* injected sequencer (ranks sequence starting from 4-JL)
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @param _RANKNB_: Rank number.
|
|
* @param _JSQR_JL_: Sequence length.
|
|
* @retval None
|
|
*/
|
|
#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
|
|
((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
|
|
|
|
/**
|
|
* @brief Enable ADC continuous conversion mode.
|
|
* @param _CONTINUOUS_MODE_: Continuous mode.
|
|
* @retval None
|
|
*/
|
|
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
|
|
((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
|
|
|
|
/**
|
|
* @brief Configures the number of discontinuous conversions for the regular group channels.
|
|
* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
|
|
* @retval None
|
|
*/
|
|
#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
|
|
(((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
|
|
|
|
/**
|
|
* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
|
|
* @param _SCAN_MODE_: Scan conversion mode.
|
|
* @retval None
|
|
*/
|
|
/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
|
|
/* is equivalent to ADC_SCAN_ENABLE. */
|
|
#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
|
|
(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
|
|
)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
|
|
)
|
|
|
|
/**
|
|
* @brief Get the maximum ADC conversion cycles on all channels.
|
|
* Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
|
|
* Approximation of sampling time within 4 ranges, returns the highest value:
|
|
* below 7.5 cycles {1.5 cycle; 7.5 cycles},
|
|
* between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
|
|
* between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
|
|
* equal to 239.5 cycles
|
|
* Unit: ADC clock cycles
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval ADC conversion cycles on all channels
|
|
*/
|
|
#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
|
|
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
|
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
|
|
\
|
|
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
|
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
|
|
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
|
|
: \
|
|
((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
|
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
|
|
((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
|
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
|
|
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
|
|
)
|
|
|
|
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
|
|
((ALIGN) == ADC_DATAALIGN_LEFT) )
|
|
|
|
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
|
|
((SCAN_MODE) == ADC_SCAN_ENABLE) )
|
|
|
|
#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
|
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
|
|
|
|
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
|
|
((CHANNEL) == ADC_CHANNEL_1) || \
|
|
((CHANNEL) == ADC_CHANNEL_2) || \
|
|
((CHANNEL) == ADC_CHANNEL_3) || \
|
|
((CHANNEL) == ADC_CHANNEL_4) || \
|
|
((CHANNEL) == ADC_CHANNEL_5) || \
|
|
((CHANNEL) == ADC_CHANNEL_6) || \
|
|
((CHANNEL) == ADC_CHANNEL_7) || \
|
|
((CHANNEL) == ADC_CHANNEL_8) || \
|
|
((CHANNEL) == ADC_CHANNEL_9) || \
|
|
((CHANNEL) == ADC_CHANNEL_10) || \
|
|
((CHANNEL) == ADC_CHANNEL_11) || \
|
|
((CHANNEL) == ADC_CHANNEL_12) || \
|
|
((CHANNEL) == ADC_CHANNEL_13) || \
|
|
((CHANNEL) == ADC_CHANNEL_14) || \
|
|
((CHANNEL) == ADC_CHANNEL_15) || \
|
|
((CHANNEL) == ADC_CHANNEL_16) || \
|
|
((CHANNEL) == ADC_CHANNEL_17) )
|
|
|
|
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
|
|
((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
|
|
((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
|
|
((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
|
|
((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
|
|
((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
|
|
((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
|
|
((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
|
|
|
|
#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_10) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_11) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_12) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_13) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_14) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_15) || \
|
|
((CHANNEL) == ADC_REGULAR_RANK_16) )
|
|
|
|
#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
|
|
|
|
#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
|
|
((CONVERSION) == ADC_INJECTED_GROUP) || \
|
|
((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
|
|
|
|
#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
|
|
|
|
|
|
/** @defgroup ADC_range_verification ADC range verification
|
|
* For a unique ADC resolution: 12 bits
|
|
* @{
|
|
*/
|
|
#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
|
|
* @{
|
|
*/
|
|
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
|
|
* @{
|
|
*/
|
|
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Include ADC HAL Extension module */
|
|
#include "stm32f1xx_hal_adc_ex.h"
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/** @addtogroup ADC_Exported_Functions
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup ADC_Exported_Functions_Group1
|
|
* @{
|
|
*/
|
|
|
|
|
|
/* Initialization and de-initialization functions **********************************/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
|
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
/* Callbacks Register/UnRegister functions ***********************************/
|
|
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
|
|
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* IO operation functions *****************************************************/
|
|
|
|
/** @addtogroup ADC_Exported_Functions_Group2
|
|
* @{
|
|
*/
|
|
|
|
|
|
/* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
|
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
|
|
|
/* Non-blocking mode: Interruption */
|
|
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
|
|
|
/* Non-blocking mode: DMA */
|
|
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
|
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
|
|
|
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
|
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
|
|
|
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
|
|
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/* Peripheral Control functions ***********************************************/
|
|
/** @addtogroup ADC_Exported_Functions_Group3
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
|
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/* Peripheral State functions *************************************************/
|
|
/** @addtogroup ADC_Exported_Functions_Group4
|
|
* @{
|
|
*/
|
|
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
|
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/* Internal HAL driver functions **********************************************/
|
|
/** @addtogroup ADC_Private_Functions
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
|
|
void ADC_StabilizationTime(uint32_t DelayUs);
|
|
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
|
|
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
|
|
void ADC_DMAError(DMA_HandleTypeDef *hdma);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
|
|
#endif /* __STM32F1xx_HAL_ADC_H */
|