154 lines
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154 lines
11 KiB
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 <span id="projectnumber">Version 5.1.2</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="textblock">Here are the data structures with brief descriptions:</div><div class="directory">
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<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionAPSR__Type.html" target="_self">APSR_Type</a></td><td class="desc">Union type to access the Application Program Status Register (APSR) </td></tr>
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<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structARM__MPU__Region__t.html" target="_self">ARM_MPU_Region_t</a></td><td class="desc">Setup information of a single MPU Region </td></tr>
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<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionCONTROL__Type.html" target="_self">CONTROL_Type</a></td><td class="desc">Union type to access the Control Registers (CONTROL) </td></tr>
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<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structCoreDebug__Type.html" target="_self">CoreDebug_Type</a></td><td class="desc">Structure type to access the Core Debug Register (CoreDebug) </td></tr>
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<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structDWT__Type.html" target="_self">DWT_Type</a></td><td class="desc">Structure type to access the Data Watchpoint and Trace Register (DWT) </td></tr>
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<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structFPU__Type.html" target="_self">FPU_Type</a></td><td class="desc">Structure type to access the Floating Point Unit (FPU) </td></tr>
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<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionIPSR__Type.html" target="_self">IPSR_Type</a></td><td class="desc">Union type to access the Interrupt Program Status Register (IPSR) </td></tr>
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<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structITM__Type.html" target="_self">ITM_Type</a></td><td class="desc">Structure type to access the Instrumentation Trace Macrocell Register (ITM) </td></tr>
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<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structMPU__Type.html" target="_self">MPU_Type</a></td><td class="desc">Structure type to access the Memory Protection Unit (MPU) </td></tr>
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<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structNVIC__Type.html" target="_self">NVIC_Type</a></td><td class="desc">Structure type to access the Nested Vectored Interrupt Controller (NVIC) </td></tr>
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<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCB__Type.html" target="_self">SCB_Type</a></td><td class="desc">Structure type to access the System Control Block (SCB) </td></tr>
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<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCnSCB__Type.html" target="_self">SCnSCB_Type</a></td><td class="desc">Structure type to access the System Control and ID Register not in the SCB </td></tr>
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<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSysTick__Type.html" target="_self">SysTick_Type</a></td><td class="desc">Structure type to access the System Timer (SysTick) </td></tr>
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<tr id="row_13_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structTPI__Type.html" target="_self">TPI_Type</a></td><td class="desc">Structure type to access the Trace Port Interface Register (TPI) </td></tr>
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<tr id="row_14_" class="even"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionxPSR__Type.html" target="_self">xPSR_Type</a></td><td class="desc">Union type to access the Special-Purpose Program Status Registers (xPSR) </td></tr>
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</table>
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<li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved.
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