159 lines
6.8 KiB
C
159 lines
6.8 KiB
C
/**
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******************************************************************************
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* @file ADC/ADC_DualModeInterleaved/Inc/main.h
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* @author MCD Application Team
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* @brief Header for main.c module
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __MAIN_H
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#define __MAIN_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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#include "stm3210c_eval.h"
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Trigger for ADC: */
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/* - If this literal is defined: ADC is operating in not continuous mode */
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/* and conversions are trigger by external trigger: timer. */
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/* - If this literal is not defined: ADC is operating in continuous mode */
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/* and first conversion is trigger by software trigger. */
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#define ADC_TRIGGER_FROM_TIMER
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/* Waveform voltage generation for test: */
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/* - If this literal is defined: For this example purpose, generates a */
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/* waveform voltage on a spare DAC channel, so user has just to connect */
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/* a wire between DAC channel output and ADC input to run this example. */
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/* (this avoid to user the need of an external signal generator). */
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/* - If this literal is not defined: User has to connect an external signal */
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/* generator on the selected ADC input to run this example. */
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#define WAVEFORM_VOLTAGE_GENERATION_FOR_TEST
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/* User can use this section to tailor ADCx instance under use and associated
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resources */
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/* ## Definition of ADC related resources ################################### */
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/* Definition of ADCx clock resources */
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#define ADCx ADC1
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#define ADCx_CLK_ENABLE() __HAL_RCC_ADC1_CLK_ENABLE()
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#define ADCx_FORCE_RESET() __HAL_RCC_ADC1_FORCE_RESET()
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#define ADCx_RELEASE_RESET() __HAL_RCC_ADC1_RELEASE_RESET()
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/* Definition of ADCx channels */
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#define ADCx_CHANNELa ADC_CHANNEL_4
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/* Definition of ADCx channels pins */
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#define ADCx_CHANNELa_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define ADCx_CHANNELa_GPIO_PORT GPIOA
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#define ADCx_CHANNELa_PIN GPIO_PIN_4
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/* Definition of ADCx DMA resources */
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#define ADCx_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
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#define ADCx_DMA DMA1_Channel1
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#define ADCx_DMA_IRQn DMA1_Channel1_IRQn
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#define ADCx_DMA_IRQHandler DMA1_Channel1_IRQHandler
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/* Definition of ADCx NVIC resources */
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#define ADCx_IRQn ADC1_2_IRQn
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#define ADCx_IRQHandler ADC1_2_IRQHandler
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/* Definition of ADCy clock resources */
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#define ADCy ADC2
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#define ADCy_CLK_ENABLE() __HAL_RCC_ADC2_CLK_ENABLE()
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#define ADCy_FORCE_RESET() __HAL_RCC_ADC2_FORCE_RESET()
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#define ADCy_RELEASE_RESET() __HAL_RCC_ADC2_RELEASE_RESET()
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/* Definition of ADCy channels */
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#define ADCy_CHANNELa ADC_CHANNEL_4
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/* Definition of ADCy channels pins */
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#define ADCy_CHANNELa_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define ADCy_CHANNELa_GPIO_PORT GPIOA
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#define ADCy_CHANNELa_PIN GPIO_PIN_4
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/* Definition of ADCy NVIC resources */
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#define ADCy_IRQn ADC1_2_IRQn
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#define ADCy_IRQHandler ADC1_2_IRQHandler
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/* #if defined(ADC_TRIGGER_FROM_TIMER) */ /* Note: Line commented for compilation purpose in HAL MSP functions */
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/* ## Definition of TIM related resources ################################### */
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/* Definition of TIMx clock resources */
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#define TIMx TIM3 /* Caution: Timer instance must be on APB1 (clocked by PCLK1) due to frequency computation in function "TIM_Config()" */
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#define TIMx_CLK_ENABLE() __HAL_RCC_TIM3_CLK_ENABLE()
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#define TIMx_FORCE_RESET() __HAL_RCC_TIM3_FORCE_RESET()
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#define TIMx_RELEASE_RESET() __HAL_RCC_TIM3_RELEASE_RESET()
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#define ADC_EXTERNALTRIGCONV_Tx_TRGO ADC_EXTERNALTRIGCONV_T3_TRGO
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/* #endif */ /* ADC_TRIGGER_FROM_TIMER */
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#if defined(WAVEFORM_VOLTAGE_GENERATION_FOR_TEST)
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/* ## Definition of DAC related resources for waveform voltage generation test ## */
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/* Definition of DACx clock resources */
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#define DACx DAC
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#define DACx_CLK_ENABLE() __HAL_RCC_DAC_CLK_ENABLE()
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#define DACx_CHANNEL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define DACx_FORCE_RESET() __HAL_RCC_DAC_FORCE_RESET()
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#define DACx_RELEASE_RESET() __HAL_RCC_DAC_RELEASE_RESET()
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/* Definition of DACx channels */
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#define DACx_CHANNELa DAC_CHANNEL_1
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/* Definition of DACx channels pins */
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#define DACx_CHANNELa_PIN GPIO_PIN_4
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#define DACx_CHANNELa_GPIO_PORT GPIOA
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/* ## Definition of TIM related resources for waveform voltage generation test ## */
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#define TIM_test_signal_generation TIM6 /* Caution: Timer instance must be on APB1 (clocked by PCLK1) due to frequency computation in function "WaveformVoltageGenerationForTest()" */
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#define TIM_test_signal_generation_CLK_ENABLE() __HAL_RCC_TIM6_CLK_ENABLE()
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#define TIM_test_signal_generation_FORCE_RESET() __HAL_RCC_TIM6_FORCE_RESET()
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#define TIM_test_signal_generation_RELEASE_RESET() __HAL_RCC_TIM6_RELEASE_RESET()
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#define DACx_TRIGGER_Tx_TRGO DAC_TRIGGER_T6_TRGO
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/* Definition of DACx DMA resources */
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#define DACx_CHANNELa_DMA_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
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#define DACx_CHANNELa_DMA DMA2_Channel3
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#define DACx_CHANNELb_DMA DMA2_Channel4
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#define DACx_CHANNELa_DMA_IRQn DMA2_Channel3_IRQn
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#define DACx_CHANNELa_DMA_IRQHandler DMA2_Channel3_IRQHandler
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#endif /* WAVEFORM_VOLTAGE_GENERATION_FOR_TEST */
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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#endif /* __MAIN_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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