{"text_format":"3","workbook":"xls","n_sheets":3,"sheets":["ADC_DualModeInterleaved","xl_DCF_History","Classified as UnClassified"],"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"ADC_DualModeInterleaved","index":0,"n_rows":51,"n_cols":80,"rows_kept":51,"merged":[[5,2,5,3],[5,4,5,5],[5,6,5,7],[5,8,5,9],[5,10,5,11],[5,12,5,13],[5,14,5,15],[5,16,5,17],[5,18,5,19],[5,20,5,21],[5,22,5,23],[5,24,5,25],[5,26,5,27],[5,28,5,29],[5,30,5,31],[5,32,5,33],[5,34,5,35],[5,36,5,37],[5,38,5,39],[5,40,5,41],[5,42,5,43],[5,44,5,45],[5,46,5,47],[5,48,5,49],[5,50,5,51],[5,52,5,53],[5,54,5,55],[5,56,5,57],[5,58,5,59],[5,60,5,61],[5,62,5,63],[5,64,5,65],[5,66,5,67],[5,68,5,69],[5,70,5,71],[5,72,5,73],[5,74,5,75],[5,76,5,77],[5,78,5,79],[7,2,7,6],[7,7,7,33],[7,34,7,38],[7,39,7,67],[7,68,7,72],[8,7,8,16],[8,39,8,48],[8,73,8,79],[9,17,9,21],[9,22,9,48],[9,49,9,53],[16,2,16,3],[16,4,16,5],[16,6,16,7],[16,8,16,9],[16,10,16,11],[16,12,16,13],[16,14,16,15],[16,16,16,17],[16,18,16,19],[16,20,16,21],[16,22,16,23],[16,24,16,25],[16,26,16,27],[16,28,16,29],[16,30,16,31],[16,32,16,33],[16,34,16,35],[16,36,16,37],[16,38,16,39],[16,40,16,41],[16,42,16,43],[16,44,16,45],[16,46,16,47],[16,48,16,49],[16,50,16,51],[16,52,16,53],[16,54,16,55],[16,56,16,57],[16,58,16,59],[16,60,16,61],[16,62,16,63],[16,64,16,65],[16,66,16,67],[16,68,16,69],[16,70,16,71],[16,72,16,73],[16,74,16,75],[16,76,16,77],[16,78,16,79],[18,2,18,6],[18,7,18,33],[18,38,18,42],[18,43,18,69],[18,74,18,78],[19,7,19,16],[19,43,19,52],[20,17,20,21],[20,22,20,48],[20,53,20,57],[29,5,29,78],[30,5,30,78],[32,5,32,78],[33,5,33,78],[35,5,35,78],[36,5,36,78],[38,5,38,78],[39,5,39,78],[41,5,41,78],[43,5,43,78]],"flags":["formulas_cached_only"]}
[]
[null,"Example \"ADC_MultimodeDualInterleaved\" for STM32L4, ADC conversions timing :"]
[]
[null,"Continuous mode:"]
[]
[null,"ADC clock cycles",0,null,1,null,2,null,3,null,4,null,5,null,6,null,7,null,8,null,9,null,10,null,11,null,12,null,13,null,14,null,15,null,16,null,17,null,18,null,19,null,20,null,21,null,22,null,23,null,24,null,25,null,26,null,27,null,28,null,29,null,30,null,31,null,32,null,33,null,34,null,35,null,36,null,37,null,38]
[null,"Conv trigger","T"]
[null,"ADC master\n(ADC1)","Sampling phase",{"$nulls":4},"Conversion\nphase",{"$nulls":26},"Sampling phase",{"$nulls":4},"Conversion\nphase",{"$nulls":28},"Sampling phase"]
[null,"Delay",{"$nulls":5},"Delay",{"$nulls":31},"Delay",{"$nulls":33},"Delay"]
[null,"ADC slave\n(ADC2)",{"$nulls":15},"Sampling phase",{"$nulls":4},"Conversion\nphase",{"$nulls":26},"Sampling phase"]
[null,"CH12data",{"$nulls":32},"A",{"$nulls":14},"A",{"$nulls":18},"A"]
[null,"DMA transfer",{"$nulls":47},"D"]
[]
[]
[null,"Not continuous mode:"]
[]
[null,"ADC clock cycles",0,null,1,null,2,null,3,null,4,null,5,null,6,null,7,null,8,null,9,null,10,null,11,null,12,null,13,null,14,null,15,null,16,null,17,null,18,null,19,null,20,null,21,null,22,null,23,null,24,null,25,null,26,null,27,null,28,null,29,null,30,null,31,null,32,null,33,null,34,null,35,null,36,null,37,null,38]
[null,"Conv trigger","T",{"$nulls":35},"T",{"$nulls":35},"T"]
[null,"ADC master\n(ADC1)","Sampling phase",{"$nulls":4},"Conversion\nphase",{"$nulls":30},"Sampling phase",{"$nulls":4},"Conversion\nphase",{"$nulls":30},"Sampling phase"]
[null,"Delay",{"$nulls":5},"Delay",{"$nulls":35},"Delay",{"$nulls":35},"Delay"]
[null,"ADC slave\n(ADC2)",{"$nulls":15},"Sampling phase",{"$nulls":4},"Conversion\nphase",{"$nulls":30},"Sampling phase"]
[null,"CH12data",{"$nulls":32},"A",{"$nulls":14},"A",{"$nulls":20},"A"]
[null,"DMA transfer",{"$nulls":47},"D"]
[]
[]
[]
[]
[{"$nulls":3},"Legend"]
[]
[{"$nulls":5},"Sampling phase"]
[{"$nulls":5},"Set by software to LL_ADC_SAMPLINGTIME_2CYCLES_5"]
[]
[{"$nulls":5},"Conversion phase"]
[{"$nulls":5},"Resolution is set by software to ADC_RESOLUTION12B, and therefore conversion phase lasts 12,5 ADC clock cycles.\nNote: Each resolution setting 6/8/10/12 bits induce different conversion cycles."]
[]
[{"$nulls":5},"Delay inserted by hardware between ADC master and ADC slave"]
[{"$nulls":5},"Delay is set by software to ADC_TWOSAMPLINGDELAY_5CYCLES\nNote: Delay has been chosen to have ADC2 conversion start in the mid-delay between ADC1 conversions"]
[]
[{"$nulls":3},"T",null,"Conversion trigger on ADC master"]
[{"$nulls":5},"Trigger either by software start or external trigger (timer, ExtI, ...)"]
[]
[{"$nulls":3},"A",null,"Converted data available in ADC common data register"]
[]
[{"$nulls":3},"D",null,"Conversion result tranfer by DMA, every ADC1+ADC2 conversions"]
[]
[]
[null,"ADC sampling rate calculation (in continuous mode):"]
[null,"There are 2 ADC conversions every 14 ADC clock cycles (sample cycles + conversion cycles)"]
[null,"This is equivalent to 1 ADC conversion every 7 ADC clock cycles."]
[null,"In this example, APB2 clock frequency is 72MHz and ADC clock prescaler is set to 1: ADC clock frequency is 72MHz"]
[null,"=> Sampling frequency is: 10.3 Msamples/sec"]

{"sheet":"xl_DCF_History","index":1,"n_rows":2,"n_cols":7,"rows_kept":2,"hidden":true,"flags":["formulas_cached_only"]}
["CLINAME","DATETIME","DONEBY","IPADDRESS","APPVER","RANDOM","CHECKSUM"]
["ᑦᑿᑔᑽᑲᒄᒄᑺᑷᑺᑶᑵ","ᑅᑀᑂᑀᑃᑁᑂᑂᐱᐱᑂᑊᑋᑃᑉᑡᑞᐱᐹᑘᑞᑥᐼᑂᑋᑁᐺ","ᑤᑥᑭᑣᑲᒀᒆᑷᐱᑹᒀᒄᑿᑺ","ᑥᑦᑟᑁᑁᑄᑇᑄ","ᑄᐿᑃᐿᑂᐿᑁ",17,"ᑅᑅᑈᑊ"]

{"sheet":"Classified as UnClassified","index":2,"n_rows":0,"n_cols":0,"rows_kept":0,"hidden":true,"flags":["formulas_cached_only"]}