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[]
[null,"Example \"ADC_DualModeInterleaved\" for STM32F1, ADC conversions timing :"]
[]
[null,"Continuous mode:"]
[]
[null,"ADC clock cycles",0,null,1,null,2,null,3,null,4,null,5,null,6,null,7,null,8,null,9,null,10,null,11,null,12,null,13,null,14,null,15,null,16,null,17,null,18,null,19,null,20,null,21,null,22,null,23,null,24,null,25,null,26,null,27,null,28,null,29,null,30]
[null,"Conv trigger","T"]
[null,"ADC master\n(ADC1)","Sampling phase",null,null,"Conversion\nphase",{"$nulls":24},"Sampling phase",null,null,"Conversion\nphase",{"$nulls":24},"Sampling phase"]
[null,"Delay","Delay",{"$nulls":27},"Delay",{"$nulls":29},"Delay"]
[null,"ADC slave\n(ADC2)",{"$nulls":14},"Sampling phase",null,null,"Conversion\nphase",{"$nulls":24},"Sampling phase"]
[null,"CH12data",{"$nulls":28},"A",{"$nulls":13},"A",{"$nulls":13},"A"]
[null,"DMA transfer",{"$nulls":42},"D"]
[]
[]
[null,"Not continuous mode:"]
[]
[null,"ADC clock cycles",0,null,1,null,2,null,3,null,4,null,5,null,6,null,7,null,8,null,9,null,10,null,11,null,12,null,13,null,14,null,15,null,16,null,17,null,18,null,19,null,20,null,21,null,22,null,23,null,24,null,25,null,26,null,27,null,28,null,29,null,30]
[null,"Conv trigger","T",{"$nulls":29},"T"]
[null,"ADC master\n(ADC1)","Sampling phase",null,null,"Conversion\nphase",{"$nulls":26},"Sampling phase",null,null,"Conversion\nphase",{"$nulls":24},"Sampling phase"]
[null,"Delay","Delay",{"$nulls":29},"Delay",{"$nulls":27},"Delay"]
[null,"ADC slave\n(ADC2)",{"$nulls":14},"Sampling phase",null,null,"Conversion\nphase",{"$nulls":26},"Sampling phase"]
[null,"CH12data",{"$nulls":28},"A",{"$nulls":13},"A",{"$nulls":15},"A"]
[null,"DMA transfer",{"$nulls":42},"D"]
[]
[]
[]
[]
[{"$nulls":3},"Legend"]
[]
[{"$nulls":5},"Sampling phase"]
[{"$nulls":5},"Set by software to ADC_SAMPLETIME_1CYCLE_5"]
[]
[{"$nulls":5},"Conversion phase"]
[{"$nulls":5},"Resolution is set by software to ADC_RESOLUTION12B, and therefore conversion phase lasts 12,5 clock cycles.\nNote: Each resolution setting 6/8/10/12 bits induce different conversion cycles."]
[]
[{"$nulls":5},"Delay inserted by hardware between ADC master and ADC slave"]
[{"$nulls":5},"On STM32F1, delay is set with multimode configuration ADC_DUALMODE_INTERLFAST (delay 7 ADC clock cyles), ADC_DUALMODE_INTERLSLOW (14 ADC clock cycles)."]
[]
[{"$nulls":3},"T",null,"Conversion trigger on ADC master"]
[{"$nulls":5},"Trigger either by software start or external trigger (timer, ExtI, ...)"]
[]
[{"$nulls":3},"A",null,"Converted data available in ADC common data register"]
[]
[{"$nulls":3},"D",null,"Conversion result tranfer by DMA, every ADC1+ADC2 conversions"]
[]
[]
[null,"ADC sampling rate calculation (in continuous mode):"]
[null,"There are 2 ADC conversions every 14 ADC clock cycles (sample cycles + conversion cycles)"]
[null,"This is equivalent to 1 ADC conversion every 7 ADC clock cycles."]
[null,"In this example, APB2 clock frequency is 72MHz and ADC clock prescaler is set to 6: ADC clock frequency is 12MHz"]
[null,"=> Sampling frequency is: 1.7 Msamples/sec"]

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["CLINAME","DATETIME","DONEBY","IPADDRESS","APPVER","RANDOM","CHECKSUM"]
["ᑦᑿᑔᑽᑲᒄᒄᑺᑷᑺᑶᑵ","ᑅᑀᑂᑀᑃᑁᑂᑂᐱᐱᑂᑊᑋᑃᑉᑡᑞᐱᐹᑘᑞᑥᐼᑂᑋᑁᐺ","ᑤᑥᑭᑣᑲᒀᒆᑷᐱᑹᒀᒄᑿᑺ","ᑥᑦᑟᑁᑁᑄᑇᑄ","ᑄᐿᑃᐿᑂᐿᑁ",17,"ᑅᑅᑈᑊ"]

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