CMSIS CMSIS (Cortex Microcontroller Software Interface Standard) ARM http://www.keil.com/pack/ Aligned pack structure with repository. The following folders are deprecated: - CMSIS/Include/ - CMSIS/DSP_Lib/ CMSIS-Core(M): 5.1.2 (see revision history for details) - Added Cortex-M1 support (beta). CMSIS-Core(A): 1.1.2 (see revision history for details) CMSIS-NN: 1.1.0 - Added new math functions. CMSIS-RTOS2: - API 2.1.3 (see revision history for details) - RTX 5.4.0 (see revision history for details) * Updated exception handling on Cortex-A CMSIS-Driver: - Flash Driver API V2.2.0 Utilities: - SVDConv 3.3.21 - PackChk 1.3.71 Updated Arm company brand. CMSIS-Core(M): 5.1.1 (see revision history for details) CMSIS-Core(A): 1.1.1 (see revision history for details) CMSIS-DAP: 2.0.0 (see revision history for details) CMSIS-NN: 1.0.0 - Initial contribution of the bare metal Neural Network Library. CMSIS-RTOS2: - RTX 5.3.0 (see revision history for details) - OS Tick API 1.0.1 CMSIS-Core(M): 5.1.0 (see revision history for details) - Added MPU Functions for ARMv8-M for Cortex-M23/M33. - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. CMSIS-Core(A): 1.1.0 (see revision history for details) - Added compiler_iccarm.h. - Added additional access functions for physical timer. CMSIS-DAP: 1.2.0 (see revision history for details) CMSIS-DSP: 1.5.2 (see revision history for details) CMSIS-Driver: 2.6.0 (see revision history for details) - CAN Driver API V1.2.0 - NAND Driver API V2.3.0 CMSIS-RTOS: - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. CMSIS-RTOS2: - API 2.1.2 (see revision history for details) - RTX 5.2.3 (see revision history for details) Devices: - Added GCC startup and linker script for Cortex-A9. - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. - Added IAR startup code for Cortex-A9 CMSIS-RTOS2: - RTX 5.2.1 (see revision history for details) CMSIS-Core(M): 5.0.2 (see revision history for details) - Changed Version Control macros to be core agnostic. - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. CMSIS-Core(A): 1.0.0 (see revision history for details) - Initial release - IRQ Controller API 1.0.0 CMSIS-Driver: 2.05 (see revision history for details) - All typedefs related to status have been made volatile. CMSIS-RTOS2: - API 2.1.1 (see revision history for details) - RTX 5.2.0 (see revision history for details) - OS Tick API 1.0.0 CMSIS-DSP: 1.5.2 (see revision history for details) - Fixed GNU Compiler specific diagnostics. CMSIS-Pack: 1.5.0 (see revision history for details) - added System Description File (*.SDF) Format CMSIS-Zone: 0.0.1 (Preview) - Initial specification draft Package Description: - added taxonomy for Cclass RTOS CMSIS-RTOS2: - API 2.1 (see revision history for details) - RTX 5.1.0 (see revision history for details) CMSIS-Core: 5.0.1 (see revision history for details) - Added __PACKED_STRUCT macro - Added uVisior support - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ - Updated template for secure main function (main_s.c) - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) CMSIS-DSP: 1.5.1 (see revision history for details) - added ARMv8M DSP libraries. CMSIS-Pack:1.4.9 (see revision history for details) - added Pack Index File specification and schema file Changed open source license to Apache 2.0 CMSIS_Core: - Added support for Cortex-M23 and Cortex-M33. - Added ARMv8-M device configurations for mainline and baseline. - Added CMSE support and thread context management for TrustZone for ARMv8-M - Added cmsis_compiler.h to unify compiler behaviour. - Updated function SCB_EnableICache (for Cortex-M7). - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType CMSIS-RTOS: - bug fix in RTX 4.82 (see revision history for details) CMSIS-RTOS2: - new API including compatibility layer to CMSIS-RTOS - reference implementation based on RTX5 - supports all Cortex-M variants including TrustZone for ARMv8-M CMSIS-SVD: - reworked SVD format documentation - removed SVD file database documentation as SVD files are distributed in packs - updated SVDConv for Win32 and Linux CMSIS-DSP: - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. - Added DSP libraries build projects to CMSIS pack. - CMSIS-Core 4.30.0 (see revision history for details) - CMSIS-DAP 1.1.0 (unchanged) - CMSIS-Driver 2.04.0 (see revision history for details) - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) - CMSIS-Pack 1.4.1 (see revision history for details) - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) - CMSIS-SVD 1.3.1 (see revision history for details) - CMSIS-Core 4.20 (see revision history for details) - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) - CMSIS-RTOS -- API 1.02 (unchanged) -- RTX 4.79 (see revision history for details) - CMSIS-SVD 1.3.0 (see revision history for details) - CMSIS-DAP 1.1.0 (extended with SWO support) - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) - CMSIS-DSP 1.4.5 (see revision history for details) - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) - CMSIS-RTOS -- API 1.02 (unchanged) -- RTX 4.78 (see revision history for details) - CMSIS-SVD 1.2 (unchanged) Adding Cortex-M7 support - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) - CMSIS-SVD 1.2 (Cortex-M7 extensions) - CMSIS-RTOS RTX 4.75 (see revision history for details) - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices - CMSIS-Driver 2.02 (incompatible update) - CMSIS-Pack 1.3 (see revision history for details) - CMSIS-DSP 1.4.2 (unchanged) - CMSIS-Core 3.30 (unchanged) - CMSIS-RTOS RTX 4.74 (unchanged) - CMSIS-RTOS API 1.02 (unchanged) - CMSIS-SVD 1.10 (unchanged) PACK: - removed G++ specific files from PACK - added Component Startup variant "C Startup" - added Pack Checking Utility - updated conditions to reflect tool-chain dependency - added Taxonomy for Graphics - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" - CMSIS-Driver 2.00 Preliminary (incompatible update) - CMSIS-Pack 1.1 Preliminary - CMSIS-DSP 1.4.2 (see revision history for details) - CMSIS-Core 3.30 (see revision history for details) - CMSIS-RTOS RTX 4.74 (see revision history for details) - CMSIS-RTOS API 1.02 (unchanged) - CMSIS-SVD 1.10 (unchanged) - CMSIS-RTOS 4.74 (see revision history for details) - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change) - CMSIS-RTOS 4.73 (see revision history for details) - CMSIS-Pack documentation has been added - CMSIS-Drivers header and documentation have been added to PACK - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged - CMSIS-RTOS Keil RTX V4.72 has been added to PACK - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged The software portions that are deployed in the application program are now under a BSD license which allows usage of CMSIS components in any commercial or open source projects. The Pack Description file Arm.CMSIS.pdsc describes the use cases The individual components have been update as listed below: - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections. - CMSIS-DSP library is optimized for more performance and contains several bug fixes. - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface. - CMSIS-SVD is unchanged. Generic Interfaces for Evaluation and Development Boards Cortex Microcontroller Software Interface Components Startup, System Setup Unified Device Drivers compliant to CMSIS-Driver Specifications File Drive Support and File System Graphical User Interface Network Stack using Internet Protocols Universal Serial Bus Stack Compiler Software Extensions Real-time Operating System The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Arm Cortex-M23 is based on the Armv8-M baseline architecture. It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller class processor based on the Armv8-M mainline architecture with Arm TrustZone security. no DSP Instructions, no Floating Point Unit, no TrustZone no DSP Instructions, no Floating Point Unit, TrustZone DSP Instructions, Single Precision Floating Point Unit, no TrustZone DSP Instructions, Single Precision Floating Point Unit, TrustZone The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling Armv8-M Baseline based device with TrustZone Armv8-M Mainline based device with TrustZone no DSP Instructions, no Floating Point Unit, TrustZone DSP Instructions, no Floating Point Unit, TrustZone no DSP Instructions, Single Precision Floating Point Unit, TrustZone DSP Instructions, Single Precision Floating Point Unit, TrustZone no DSP Instructions, Double Precision Floating Point Unit, TrustZone DSP Instructions, Double Precision Floating Point Unit, TrustZone The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, an optional integrated GIC, and an optional L2 cache controller. The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java bytecodes in Jazelle state. Device interrupt controller interface RTOS Kernel system tick timer interface CMSIS-RTOS API for Cortex-M, SC000, and SC300 CMSIS-RTOS API for Cortex-M, SC000, and SC300 USART Driver API for Cortex-M SPI Driver API for Cortex-M SAI Driver API for Cortex-M I2C Driver API for Cortex-M CAN Driver API for Cortex-M Flash Driver API for Cortex-M MCI Driver API for Cortex-M NAND Flash Driver API for Cortex-M Ethernet MAC and PHY Driver API for Cortex-M Ethernet MAC Driver API for Cortex-M Ethernet PHY Driver API for Cortex-M USB Device Driver API for Cortex-M USB Host Driver API for Cortex-M Armv6-M architecture based device Armv7-M architecture based device Armv8-M architecture based device Armv8-M architecture based device with TrustZone Armv6_7-M architecture based device Armv6_7_8-M architecture based device Armv7-A architecture based device Cortex-M0 or Cortex-M0+ or SC000 processor based device Cortex-M1 Cortex-M3 or SC300 processor based device Cortex-M4 processor based device Cortex-M4 processor based device using Floating Point Unit Cortex-M7 processor based device Cortex-M7 processor based device using Floating Point Unit Cortex-M7 processor based device using Floating Point Unit (SP) Cortex-M7 processor based device using Floating Point Unit (DP) Cortex-M23 processor based device Cortex-M33 processor based device Cortex-M33 processor based device using Floating Point Unit Armv8-M Baseline processor based device Armv8-M Mainline processor based device Armv8-M Mainline processor based device using Floating Point Unit CM33, no DSP, no FPU CM33, DSP, no FPU CM33, no DSP, SP FPU CM33, DSP, SP FPU Armv8-M Mainline, no DSP, no FPU Armv8-M Mainline, DSP, no FPU Armv8-M Mainline, no DSP, SP FPU Armv8-M Mainline, DSP, SP FPU Cortex-A5 or Cortex-A9 processor based device Cortex-A7 processor based device Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5 Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6 Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler Cortex-M1 based device for the Arm Compiler Cortex-M1 based device in little endian mode for the Arm Compiler Cortex-M1 based device in big endian mode for the Arm Compiler Cortex-M3 or SC300 processor based device for the Arm Compiler Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler Cortex-M4 processor based device for the Arm Compiler Cortex-M4 processor based device in little endian mode for the Arm Compiler Cortex-M4 processor based device in big endian mode for the Arm Compiler Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler Cortex-M7 processor based device for the Arm Compiler Cortex-M7 processor based device in little endian mode for the Arm Compiler Cortex-M7 processor based device in big endian mode for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler Cortex-M23 processor based device for the Arm Compiler Cortex-M23 processor based device in little endian mode for the Arm Compiler Cortex-M23 processor based device in big endian mode for the Arm Compiler Cortex-M33 processor based device for the Arm Compiler Cortex-M33 processor based device in little endian mode for the Arm Compiler Cortex-M33 processor based device in big endian mode for the Arm Compiler Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler Cortex-M33 processor, no DSP, no FPU, Arm Compiler Cortex-M33 processor, DSP, no FPU, Arm Compiler Cortex-M33 processor, no DSP, SP FPU, Arm Compiler Cortex-M33 processor, DSP, SP FPU, Arm Compiler Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler Armv8-M Baseline processor based device for the Arm Compiler Armv8-M Baseline processor based device in little endian mode for the Arm Compiler Armv8-M Baseline processor based device in big endian mode for the Arm Compiler Armv8-M Mainline processor based device for the Arm Compiler Armv8-M Mainline processor based device in little endian mode for the Arm Compiler Armv8-M Mainline processor based device in big endian mode for the Arm Compiler Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler Armv8-M Mainline processor based device using Floating Point Unit in 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endian mode for the GCC Compiler Cortex-M1 based device in big endian mode for the GCC Compiler Cortex-M3 or SC300 processor based device for the GCC Compiler Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler Cortex-M4 processor based device for the GCC Compiler Cortex-M4 processor based device in little endian mode for the GCC Compiler Cortex-M4 processor based device in big endian mode for the GCC Compiler Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler Cortex-M7 processor based device for the GCC Compiler Cortex-M7 processor based device in little endian mode for the GCC Compiler Cortex-M7 processor based device in big endian mode for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler Cortex-M23 processor based device for the GCC Compiler Cortex-M23 processor based device in little endian mode for the GCC Compiler Cortex-M23 processor based device in big endian mode for the GCC Compiler Cortex-M33 processor based device for the GCC Compiler Cortex-M33 processor based device in little endian mode for the GCC Compiler Cortex-M33 processor based device in big endian mode for the GCC Compiler Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler CM33, no DSP, no FPU, GCC Compiler CM33, DSP, no FPU, GCC Compiler CM33, no DSP, SP FPU, GCC Compiler CM33, DSP, SP FPU, GCC Compiler CM33, little endian, no DSP, no FPU, GCC Compiler CM33, little endian, DSP, no FPU, GCC Compiler CM33, little endian, no DSP, SP FPU, GCC Compiler CM33, little endian, DSP, SP FPU, GCC Compiler Armv8-M Baseline processor based device for the GCC Compiler Armv8-M Baseline processor based device in little endian mode for the GCC Compiler Armv8-M Baseline processor based device in big endian mode for the GCC Compiler Armv8-M Mainline processor based device for the GCC Compiler Armv8-M Mainline processor based device in little endian mode for the GCC Compiler Armv8-M Mainline processor based device in big endian mode for the GCC Compiler Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler Armv8-M Mainline, no DSP, no FPU, GCC Compiler Armv8-M Mainline, DSP, no FPU, GCC Compiler Armv8-M Mainline, no DSP, SP FPU, GCC Compiler Armv8-M Mainline, DSP, SP FPU, GCC Compiler Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler Cortex-M1 based device for the IAR Compiler Cortex-M1 based device in little endian mode for the IAR Compiler Cortex-M1 based device in big endian mode for the IAR Compiler Cortex-M3 or SC300 processor based device for the IAR Compiler Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler Cortex-M4 processor based device for the IAR Compiler Cortex-M4 processor based device in little endian mode for the IAR Compiler Cortex-M4 processor based device in big endian mode for the IAR Compiler Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler Cortex-M7 processor based device for the IAR Compiler Cortex-M7 processor based device in little endian mode for the IAR Compiler Cortex-M7 processor based device in big endian mode for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler Cortex-M23 processor based device for the IAR Compiler Cortex-M23 processor based device in little endian mode for the IAR Compiler Cortex-M23 processor based device in big endian mode for the IAR Compiler Cortex-M33 processor based device for the IAR Compiler Cortex-M33 processor based device in little endian mode for the IAR Compiler Cortex-M33 processor based device in big endian mode for the IAR Compiler Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler CM33, no DSP, no FPU, IAR Compiler CM33, DSP, no FPU, IAR Compiler CM33, no DSP, SP FPU, IAR Compiler CM33, DSP, SP FPU, IAR Compiler CM33, little endian, no DSP, no FPU, IAR Compiler CM33, little endian, DSP, no FPU, IAR Compiler CM33, little endian, no DSP, SP FPU, IAR Compiler CM33, little endian, DSP, SP FPU, IAR Compiler Armv8-M Baseline processor based device for the IAR Compiler Armv8-M Baseline processor based device in little endian mode for the IAR Compiler Armv8-M Baseline processor based device in big endian mode for the IAR Compiler Armv8-M Mainline processor based device for the IAR Compiler Armv8-M Mainline processor based device in little endian mode for the IAR Compiler Armv8-M Mainline processor based device in big endian mode for the IAR Compiler Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler Armv8-M Mainline, no DSP, no FPU, IAR Compiler Armv8-M Mainline, DSP, no FPU, IAR Compiler Armv8-M Mainline, no DSP, SP FPU, IAR Compiler Armv8-M Mainline, DSP, SP FPU, IAR Compiler Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler Generic Arm Cortex-M0 device startup and depends on CMSIS Core Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC Generic Arm Cortex-M0+ device startup and depends on CMSIS Core Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC Generic Arm Cortex-M1 device startup and depends on CMSIS Core Generic ARM Cortex-M1 device startup and depends on CMSIS Core requiring GCC Generic Arm Cortex-M3 device startup and depends on CMSIS Core Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC Generic Arm Cortex-M4 device startup and depends on CMSIS Core Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC Generic Arm Cortex-M7 device startup and depends on CMSIS Core Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC Generic Arm Cortex-M23 device startup and depends on CMSIS Core Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC Generic Arm Cortex-M33 device startup and depends on CMSIS Core Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC Generic Arm SC000 device startup and depends on CMSIS Core Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC Generic Arm SC300 device startup and depends on CMSIS Core Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC Generic Armv8-M Baseline device startup and depends on CMSIS Core Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC Generic Armv8-M Mainline device startup and depends on CMSIS Core Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC Generic Arm Cortex-A5 device startup and depends on CMSIS Core Generic Arm Cortex-A7 device startup and depends on CMSIS Core Generic Arm Cortex-A9 device startup and depends on CMSIS Core Components required for DSP Components required for NN Components required for RTOS RTX Components required for RTOS RTX IFX Components required for RTOS RTX5 Components required for RTOS2 RTX5 Components required for RTOS2 RTX5 on Armv7-A Components required for RTOS2 RTX5 Library Components required for RTOS2 RTX5 in Non-Secure Domain Components required for OS Tick Private Timer Components required for OS Tick Generic Physical Timer CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M CMSIS-CORE for Cortex-A System and Startup for Generic Arm Cortex-M0 device System and Startup for Generic Arm Cortex-M0 device System and Startup for Generic Arm Cortex-M0+ device System and Startup for Generic Arm Cortex-M0+ device System and Startup for Generic Arm Cortex-M1 device System and Startup for Generic Arm Cortex-M1 device System and Startup for Generic Arm Cortex-M3 device System and Startup for Generic Arm Cortex-M3 device System and Startup for Generic Arm Cortex-M4 device System and Startup for Generic Arm Cortex-M4 device System and Startup for Generic Arm Cortex-M7 device System and Startup for Generic Arm Cortex-M7 device System and Startup for Generic Arm Cortex-M23 device System and Startup for Generic Arm Cortex-M23 device System and Startup for Generic Arm Cortex-M33 device System and Startup for Generic Arm Cortex-M33 device System and Startup for Generic Arm SC000 device System and Startup for Generic Arm SC000 device System and Startup for Generic Arm SC300 device System and Startup for Generic Arm SC300 device System and Startup for Generic Armv8-M Baseline device System and Startup for Generic Armv8-M Baseline device System and Startup for Generic Armv8-M Mainline device System and Startup for Generic Armv8-M Mainline device System and Startup for Generic Arm Cortex-A5 device System and Startup for Generic Arm Cortex-A7 device System and Startup for Generic Arm Cortex-A9 device IRQ Controller implementation using GIC OS Tick implementation using Private Timer OS Tick implementation using Generic Physical Timer CMSIS-DSP Library for Cortex-M, SC000, and SC300 CMSIS-NN Neural Network Library CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */ CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ CMSIS-RTOS2 RTX5 for Armv7-A (Source) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ uVision Simulator Fixed Virtual Platform DSP_Lib Class Marks example Getting Started DSP_Lib Convolution example Getting Started DSP_Lib Dotproduct example Getting Started DSP_Lib FFT Bin example Getting Started DSP_Lib FIR example Getting Started DSP_Lib Graphic Equalizer example Getting Started DSP_Lib Linear Interpolation example Getting Started DSP_Lib Matrix example Getting Started DSP_Lib Signal Convergence example Getting Started DSP_Lib Sinus/Cosinus example Getting Started DSP_Lib Variance example Getting Started Neural Network CIFAR10 example Getting Started Neural Network GRU example Getting Started CMSIS-RTOS2 Blinky example Getting Started CMSIS-RTOS2 mixed API v1 and v2 Getting Started CMSIS-RTOS2 Message Queue Example Getting Started CMSIS-RTOS2 Memory Pool Example Getting Started Bare-metal secure/non-secure example without RTOS Getting Started Secure/non-secure RTOS example with thread context management Getting Started Secure/non-secure RTOS example with security test cases and system recovery Getting Started