In dm00031020, chapter 32.9.4, it is said that the register can take values up to 28 in order to have all filters assigned to can1.
However, in stm32F1XX_hal_can.h, the define IS_CAN_FILTER_BANK_DUAL tests it to be <=27.
I do believe this test is wrong and will fail a valid call to set filters if asserts are enabled.
For parts like the STM32F1 Connectivity Line (STM32F105xx, STM32F107xx),
it is occasionally necessary to source SYSCLK via PLL2. This patch will
add this support.
- Add: `UTILS_GetPLL2OutputFrequency()` to calculate the output frequency of PLL2
- Add: `LL_PLL_ConfigSystemClock_PLL2()` to configure the system clock as sourced from HSE, via PLL2 and PLL1.
- Add: Miscellaneous support definitions.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Frederic Barachant
deividAlfa
Eya
Maerdl
Attie Grande
rihab kouki